AT91SAM9260-EK Atmel, AT91SAM9260-EK Datasheet
AT91SAM9260-EK
Specifications of AT91SAM9260-EK
Related parts for AT91SAM9260-EK
AT91SAM9260-EK Summary of contents
Page 1
... I/O – Three 32-bit Parallel Input/Output Controllers – 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os • Package – 217-ball BGA, 0.8 mm pitch – 208-pin QFP, 0.5 mm pitch ® Processor AT91 ARM Thumb Microcontrollers AT91SAM9260 Summary 6221JS–ATARM–17-Jul-09 ...
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... The AT91SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The AT91SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host control- ler. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface ...
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... Figure 2-1. AT91SAM9260 Block Diagram 6221JS–ATARM–17-Jul-09 Filter AT91SAM9260 3 ...
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... Wake-up Input NTRST Test Reset Signal TCK Test Clock TDI Test Data In TDO Test Data Out TMS Test Mode Select JTAGSEL JTAG Selection RTCK Return Test Clock AT91SAM9260 4 Active Type Power Supplies Power Power Power Power Power Power Power Ground Ground Ground ...
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... Output Output Output Output CompactFlash Support Output Output Output Output Output Output Output AT91SAM9260 Active Level Comments Low Pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. No pull-up resistor BMS = 0 when tied to GND BMS = 1 when tied to VDDIOP0. Pulled-up input at reset Pulled-up input at reset ...
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... RI0 USART0 Ring Indicator TD SSC Transmit Data RD SSC Receive Data TK SSC Transmit Clock RK SSC Receive Clock TF SSC Transmit Frame Sync RF SSC Receive Frame Sync AT91SAM9260 6 Type NAND Flash Support Output Output Output Output Output SDRAM Controller Output Output Output Output Output ...
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... Input Input Output Output Output Input Input Input Input Input Output I/O Output AT91SAM9260 Active Level Comments Low Low MII only, REFCK in RMII MII only ETX0-ETX1 only in RMII MII only RXDV in MII , CRSDV in RMII ERX0-ERX1 only in RMII MII only MII only ...
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... ISI_HSYNC Image Sensor Horizontal Synchro ISI_VSYNC Image Sensor Vertical Synchro ISI_PCK Image Sensor Data clock AD0-AD3 Analog Inputs ADVREF Analog Positive Reference ADTRG ADC Trigger AT91SAM9260 8 Active Type Level Image Sensor Interface Input Output Input Input Input Analog to Digital Converter Analog ...
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... LFBGA Green package (0.8 mm ball pitch) 4.1 208-pin PQFP Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Character- istics” of the product datasheet. Figure 4-1. 6221JS–ATARM–17-Jul-09 shows the orientation of the 208-pin PQFP package. ...
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... BMS 92 41 OSCSEL 93 42 TST 94 43 JTAGSEL 95 44 GNDBU 96 45 XOUT32 97 46 XIN32 98 47 VDDBU 99 48 WKUP 100 AT91SAM9260 10 Signal Name Pin Signal Name GND 105 RAS DDM 106 D0 DDP 107 D1 PC13 108 D2 PC11 109 D3 PC10 110 D4 PC14 111 D5 PC9 112 ...
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... HDMA 102 51 HDPA 103 52 VDDIOP0 104 4.3 217-ball LFBGA Package Outline Figure 4-2 A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Character- istics” of the product datasheet. Figure 4-2. 6221JS–ATARM–17-Jul-09 Signal Name Pin CFIOW/NBS3/NWR3 153 CFIOR/NBS1/NWR1 154 SDCS/NCS1 155 ...
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... BA1/A17 H8 C9 A19 H9 C10 NANDOE H10 C11 PC9 H14 C12 PC12 H15 C13 DDP H16 C14 HDMB H17 C15 NC J1 AT91SAM9260 12 Signal Name Pin Signal Name A5 J14 TDO GND J15 PB19 A10 J16 TDI GND J17 PB16 VDDCORE K1 PC24 GND K2 PC20 ...
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... GNDBU, GNDPLL and GNDANA. 5.2 Power Consumption The AT91SAM9260 consumes about 500 µA of static current on VDDCORE at 25°C. This static current rises the temperature increases to 85°C. On VDDBU, the current does not exceed 10 µA in worst case conditions. ...
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... NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value can be found in the table “DC Characteristics” in the section “AT91SAM9260 Electrical Charac- teristics” in the product datasheet. The NRST signal is inserted in the Boundary Scan. ...
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... MΩ. The resistor value is calculated according to the regulator enable implementation and the SHDN level. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. 6.7 Slow Clock Selection The AT91SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or the on-chip RC oscillator. Table 6-1 Table 6-1. OSCSEL ...
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... Breaking with Slot Cycle Limit Support – Undefined Burst Length Support • One Address Decoder provided per Master – Three different slaves may be assigned to each decoded memory area: one for AT91SAM9260 16 each quarter of the page system flexibility 32-bit data interface ...
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... Matrix Masters The Bus Matrix of the AT91SAM9260 manages six Masters, which means that each master can perform an access concurrently with others, according the slave it accesses is available. Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
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... USART4 Receive Channel – USART3 Receive Channel – USART2 Receive Channel – USART1 Receive Channel – USART0 Receive Channel – ADC Receive Channel – SPI1 Receive Channel AT91SAM9260 18 AT91SAM9260 Masters to Slaves Access Internal SRAM X 4 KBytes Internal ROM X UHP User Interface X X ...
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... Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 6221JS–ATARM–17-Jul-09 AT91SAM9260 19 ...
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... Memories Figure 8-1. AT91SAM9260 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI 256M Bytes Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI 256M Bytes Chip Select 1/ SDRAMC 0x2FFF FFFF 0x3000 0000 EBI 256M Bytes ...
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... Internal Memory Mapping for each Master, depending on the Remap Internal Memory Mapping REMAP = 0 Address BMS = 1 ROM Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in AT91SAM9260 for details. 20. REMAP = 1 BMS = 0 EBI_NCS0 SRAM0 4K Figure 8-1 on page 20 ...
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... The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface ...
Page 23
... Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities – Self-refresh, power down and deep power down modes supported 6221JS–ATARM–17-Jul-09 AT91SAM9260 23 ...
Page 24
... ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes AT91SAM9260 24 detected erroneous pages ...
Page 25
... System Controller can be addressed from a single pointer by using the stan- dard ARM instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes. Figure 9-1 on page 26 Figure 8-1 on page 20 peripherals. 6221JS–ATARM–17-Jul-09 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller AT91SAM9260 25 ...
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... Block Diagram Figure 9-1. AT91SAM9260 System Controller Block Diagram irq0-irq2 periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP RC OSC OSC_SEL SLOW XIN32 CLOCK OSC XOUT32 XIN MAIN OSC ...
Page 27
... Supports MHz crystals • Embeds 2 PLLs – PLLA outputs 80 to 240 MHz clock – PLLB outputs 70 to 130 MHz clock – Both integrate an input divider to increase output accuracy – PLLB embeds its own filter 6221JS–ATARM–17-Jul-09 reset, user reset or watchdog reset AT91SAM9260 27 ...
Page 28
... Idle Mode, processor stopped waiting for an interrupt – Slow Clock Mode, processor and peripherals running at low frequency – Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, – Backup Mode, Main Power Supplies off, VDDBU powered by a battery AT91SAM9260 28 Clock Generator Block Diagram OSC_SEL ...
Page 29
... Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) 6221JS–ATARM–17-Jul-09 AT91SAM9260 Power Management Controller Block Diagram Master Clock Controller SLCK Prescaler MAINCK /1,/2,/4, ...
Page 30
... Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 9.12 Chip Identification • Chip ID: 0x019803A2 • JTAG ID: 0x05B1303F • ARM926 TAP ID: 0x0792603F AT91SAM9260 30 enabled processor Generator the ARM Processor’s ICE Interface ® ...
Page 31
... Peripheral Identifiers of the AT91SAM9260. A peripheral identifier is AT91SAM9260 Peripheral Identifiers Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC ADC US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC - - TC0 TC1 TC2 UHP EMAC ISI US3 US4 US5 TC3 ...
Page 32
... IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.3 Peripheral Signal Multiplexing on I/O Lines The AT91SAM9260 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions ...
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... I/O ETX2 I/O ETX3 I/O ERX2 I/O ERX3 I/O ERXCK I/O ECRS I/O ECOL I/O RXD4 I/O TXD4 I/O AT91SAM9260 Application Usage Power Supply Function Comments VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 ...
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... ISI_D6 PB27 CTS0 ISI_D7 PB28 RTS1 ISI_PCK PB29 CTS1 ISI_VSYNC PB30 PCK0 ISI_HSYNC PB31 PCK1 Note: 1. Not available in the 208-lead PQFP package. AT91SAM9260 34 Application Usage Comments Reset State Power Supply I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O ...
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... SPI1_NPCS1 I/O SPI1_NPCS2 I/O SPI1_NPCS3 I/O EF100 I/O TCLK5 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AT91SAM9260 Application Usage Power Supply Function Comments VDDANA VDDANA VDDANA VDDANA VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM ...
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... Optional Multi-drop Mode with address generation and detection • RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation AT91SAM9260 36 peripherals Sensors and data per chip select ...
Page 37
... Remote Loopback, Local Loopback, Automatic Echo The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the AT91SAM9260, only the USART0 implements these signals, named DTR0, DSR0, DCD0 and RI0. The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features ...
Page 38
... Interrupt generation to signal receive and transmit completion • 28-byte transmit and 28-byte receive FIFOs • Automatic pad and CRC generation on transmitted frames • Address checking logic to recognize four 48-bit addresses • Support promiscuous mode where all valid frames are copied to memory AT91SAM9260 38 6221JS–ATARM–17-Jul-09 ...
Page 39
... Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four analog inputs shared with digital signals 6221JS–ATARM–17-Jul-09 AT91SAM9260 39 ...
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... AT91SAM9260 Mechanical Characteristics 11.1 Package Drawings Figure 11-1. 217-ball LFBGA Package Drawing Table 11-1. Soldering Informations Ball Land Soldering Mask Opening Table 11-2. Device and 217-ball LFBGA Package Maximum Weight 450 Table 11-3. 217-ball LFBGA Package Characteristics Moisture Sensitivity Level Table 11-4. ...
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... Figure 11-2. 208-lead PQFP Package Drawing Table 11-5. Device and 208-lead PQFP Package Maximum Weight 5.5 Table 11-6. 208-lead PQFP Package Characteristics Moisture Sensitivity Level Table 11-7. Package Reference JEDEC Drawing Reference JESD97 Classification 6221JS–ATARM–17-Jul-09 AT91SAM9260 g 3 MS-022 e3 41 ...
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... Time within 5° Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25° Peak Temperature Note: A maximum of three reflow passes is allowed per component. AT91SAM9260 42 gives the recommended soldering profile from J-STD-20. Soldering Profile It is recommended to apply a soldering temperature higher than 250°C BGA217 Green ...
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... AT91SAM9260 Ordering Information Table 12-1. AT91SAM9260 Ordering Information Marketing Revision Level A Marketing Revision Level B Ordering Code AT91SAM9260-QU AT91SAM9260-CU 6221JS–ATARM–17-Jul-09 Ordering Code Package AT91SAM9260B-QU PQFP208 AT91SAM9260B-CU BGA217 AT91SAM9260 Temperature Operating Package Type Range Green Industrial -40°C to 85°C Green 43 ...
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... Synchronous/Asynchronous Receiver Transmitters (USART)” on page 2 Section 6.6 ”Shutdown Logic Pins” on page 15 Features list shortened and reorganized, from new structure in Datasheet AT91SAM9G45 6221IS Section 12. ”AT91SAM9260 Ordering Information” on page 43 Version B added. Table 3-1, “Signal Description List” comments. Table 10-3, “Multiplexing on PIO Controller B” ...
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... Updated information on programmable pull-up resistor in page 15 . Section 6.7 ”Slow Clock Selection” on page 15 Updated 6221ES Table 10-1, “AT91SAM9260 Peripheral Identifiers,” on page 31 In clocking and corrected Peripheral Name for PID12, PID13 and PID14. Placed comment on RDY/BUSY with PC13 in C,” on page 35 Removed references to VDDOSC in Section 5.1 ” ...
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... AT91SAM9260 46 6221JS–ATARM–17-Jul-09 ...
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