AT91SAM9260-EK Atmel, AT91SAM9260-EK Datasheet - Page 44

• Manufacturer Part Number: AT91SAM9260-EK
• Description: KIT EVAL FOR AT91SAM9260
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9260-EK

• Contents: Evaluation Board, Parallel Cable and CD-ROM
• Processor To Be Evaluated: AT91SAM9260
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB
• Core: ARM 9
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: ARM926EJ-S
• Silicon Core Number: AT91SAM9260
• Silicon Family Name: ARM
• Kit Contents: Board, Cables, CD, Power Supply
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM9260
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13. Revision History
Table 13-1.
44
Revision
6221JS
6221IS
6221HS
6221GS
6221FS
AT91SAM9260
Revision History - current version appears first
Comments
Line added to
Note edited after
‘Manchester Encoding/Decoding’ removed from
Synchronous/Asynchronous Receiver Transmitters (USART)” on page 2
Section 6.6 ”Shutdown Logic Pins” on page 15
Features list shortened and reorganized, from new structure in Datasheet AT91SAM9G45
Section 12. ”AT91SAM9260 Ordering Information” on page 43
Version B added.
Table 3-1, “Signal Description List”
comments.
Table 10-3, “Multiplexing on PIO Controller B”
Table 3-1, “Signal Description List”
”Power Considerations”
voltage restraints removed.
Updated all references to 217-ball LFBGA to Green package.
In
supply voltage during startup.
In
In
oscillator.
In
compatibility.
In
ignored.”
Changed divider value for Master Clock Controller in
Management Controller Block Diagram” on page
Corrected package reference to PQFP in
Drawing,” on page 41
Updated BGA ordering code in
780.
All new information in
on page 18
Slaves Access,” on page
In
NWR1, NWR3.
Added details on Timer/Counter blocks in
Updated Chip ID in
Section 5.1 “Power Supplies” on page
Section 6.5 “I/O Line Drive Levels” on page
Section 6.7 “Slow Clock Selection” on page
Section 10.4.6 “Multimedia Card Interface” on page
Section 8.1.1 “Boot Strategies” on page
Figure 2-1 ”AT91SAM9260 Block Diagram” on page
and
• ”Debug Unit (DBGU)” on page 2
Section 7.2.3 ”Master to Slave
Table 10-1, “AT91SAM9260 Peripheral Identifiers” on page 31
Section 9.12 ”Chip Identification” on page
Section 7.2.1 ”Matrix
.
18.
,in
Section 5.1 ”Power Supplies”
Section 43. ”AT91SAM9260 Ordering Information” on page
, Image Sensor Interface, ISI_MCK line, added
, Reset/Test, BMS line, added comments.
14, VDDCORE and VDDBU, added information on
Figure 11-2, “208-lead PQFP Package
Section 10.4.5 ”Timer Counter” on page
22, removed sentence “When REMAP = 1, BMS is
Masters”,
16, added information on PC4 to PC31.
16, corrected startup delay for internal RC
Access”,
Section • ”Four Universal
30.
, PB31 line, removed ISI_MCK.
edited
Figure 9-3, ”AT91SAM9260 Power
Table 7-1, “List of Bus Matrix Masters,”
38, corrected specification version
4, updated EBI signals NRD, NWR0,
Table 7-3, “AT91SAM9260 Masters to
, VDDCORE and VDDBU startup
32.
, New Ordering codes for
38.
6221JS–ATARM–17-Jul-09
Change
Req. Ref.
5846
5854
5933
6030
RFO
5686
5330
5422
5229
Review
Review
Review
Review
4944
5026
4833
4740
4768
4457
4431
4369
4582