C8051F120DK Silicon Laboratories Inc, C8051F120DK Datasheet - Page 251
![DEVKIT-F120/21/22/23/24/25/26/27](/photos/9/20/92070/c8051f120dk_sml.jpg)
C8051F120DK
Manufacturer Part Number
C8051F120DK
Description
DEVKIT-F120/21/22/23/24/25/26/27
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F120DK.pdf
(350 pages)
Specifications of C8051F120DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120, 121, 122, 123, 124, 125, 126, 127
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1224
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F120DK
Manufacturer:
SiliconL
Quantity:
4
- Current page: 251 of 350
- Download datasheet (2Mb)
Note:
Bits7–0: P2MDOUT.[7:0]: Port2 Output Mode Bits.
Bits7–0: P3.[7:0]: Port3 Output Latch Bits.
Note:
P3.7
R/W
R/W
Bit7
Bit7
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P3MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P3.n pin is logic low.
1: P3.n pin is logic high.
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are
always configured as Open-Drain when they appear on Port pins.
P3.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed
mode, or as D[7:0] in Non-multiplexed mode). See
Interface and On-Chip XRAM” on page 219
Interface.
P3.6
R/W
R/W
Bit6
Bit6
SFR Definition 18.10. P2MDOUT: Port2 Output Mode
P3.5
R/W
R/W
Bit5
Bit5
SFR Definition 18.11. P3: Port3 Data
P3.4
R/W
R/W
Bit4
Bit4
Rev. 1.4
P3.3
R/W
R/W
Bit3
Bit3
C8051F120/1/2/3/4/5/6/7
for more information about the External Memory
P3.2
R/W
R/W
Bit2
Bit2
Section “17. External Data Memory
C8051F130/1/2/3
P3.1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
P3.0
R/W
R/W
Bit0
Bit0
0xA6
F
0xB0
All Pages
00000000
Addressable
Reset Value
Reset Value
11111111
Bit
251
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