DV164136 Microchip Technology, DV164136 Datasheet - Page 4

• Manufacturer Part Number: DV164136
• Description: DEVELOPMENT KIT FOR PIC18
• Manufacturer: Microchip Technology
• Series: PIC®r
• Type: MCUr

Specifications of DV164136

• Contents: Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
• Processor To Be Evaluated: PIC18F8722, PIC18F87J11
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3.3 V, 5 V
• Silicon Manufacturer: Microchip
• Core Architecture: PIC
• Core Sub-architecture: PIC18
• Silicon Core Number: PIC18F
• Silicon Family Name: PIC18F8xxx
• Kit Contents: PIC18 Exp Brd PICkit 3 Cable CD PSU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC18F8722, PIC18F87J11
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J11 FAMILY
4. Module: SRAM
TABLE 3:
DS80495C-page 4
Voltage Regulator Enabled
Temperature = 25°C
SEC_RUN mode using 32 kHz Timer1 Crystal
No RAM access
Typ RAM access
Extreme RAM access
Voltage Regulator Disabled
V
Temperature = 25°C
SEC_RUN mode using 32 kHz Timer1 Crystal
No RAM access
Typ RAM access
Extreme RAM access
Note 1:
DDCORE
Any access to SRAM, either in the form of read
or write operations, will increase the current con-
sumption of the device, depending on how often
the SRAM is accessed. A small current increase
is normal, but in this cited silicon revision, the
difference may be significant and of particular
concern for low-power applications.
For further details, see Table 3.
Work around
None.
Affected Silicon Revisions
A1
2:
3:
X
Condition
Condition
is tied to V
Code execution patterns where no instructions
access SRAM.
Code execution that accesses SRAM once
every seven instruction cycles.
Code execution where every instruction cycle
executes an instruction that accesses SRAM.
A2
TYPICAL CURRENT
CONSUMPTION
(1)
(1)
(2)
(2)
A4
DD
(3)
(3)
Case 1:
Case 2:
A5
I
I
DD
DD
201
906
132
723
59
20
(A)
(A)
A6
B0
V
2.5
2.5
2.5
(V)
DD
V
DD
3.3
3.3
3.3
V
(V)
DDCORE
(V)
2.5
2.5
2.5
5. Module: Low-Voltage Detect
6. Module: MSSPx (I
The LVDSTAT, V
is not implemented in this revision of silicon.
Work around
None.
Affected Silicon Revisions
If the module is in I
slave performs clock stretching, the first clock
pulse after the slave releases the SCLx line may
be narrower than the configured clock width.
This may result in the slave missing the first
clock in the next transmission/reception.
Work around
If the module is in I
the slave to perform clock stretching. Alter-
nately, the master can slow down the SCLx
clock frequency to a level where the slave can
detect the narrowed clock pulse.
Affected Silicon Revisions
A1
A1
X
X
A2
A2
X
A4
A4
X
DDCORE
2
 2010 Microchip Technology Inc.
C Master mode, do not allow
A5
A5
2
X
2
C Master mode, and the
C™ Master)
status bit (WDTCON<6>),
A6
A6
X
B0
B0
X