CT-161-CD Fujitsu Semiconductor America Inc, CT-161-CD Datasheet - Page 32

• Manufacturer Part Number: CT-161-CD
• Description: KIT 16LX FOR MB90F387
• Manufacturer: Fujitsu Semiconductor America Inc
• Series: F²MC-16LXr
• Type: MCUr

Specifications of CT-161-CD

• Contents: Board, Cable, CD
• For Use With/related Products: MB90F387S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1103

32
MB90385 Series
3. Watchdog Timer
Interval timer of watchdog timer
Notes: If the time-base timer is cleared when watchdog timer count clock is used as time base timer output
Approx. 14.33 ms Approx. 18.3 ms
Approx. 57.23 ms Approx. 73.73 ms
Watchdog timer functions
Approx. 3.58 ms
The watchdog timer is a 2-bit counter that uses time-base timer or clock timer as count clock. If the counter is
not cleared within an interval time, CPU is reset.
• The watchdog timer is a timer counter that prevents runaway of a program. Once a watchdog timer is activated,
• The interval time of a watchdog timer is determined by a clock cycle, which is input as a count clock. Watchdog
• The output target of a clock source is specified by the watchdog clock selection bit (WTC: WDCS) in the clock
• Interval time of a watchdog timer is specified by the time-base timer output selection bit/clock timer output
HCLK: Oscillation clock ( 4 MHz) , CSCLK: Sub clock (8.192 kHz)
458.75 ms
the counter of watchdog timer must always be cleared within a specified time of interval. If specified interval
time elapses without clearing the counter of a watchdog timer, CPU resetting occurs. This is the function of a
watchdog timer.
resetting occurs between a minimum time and a maximum time specified.
timer control register.
selection bit (WDTC: WT1, WT0) in the watchdog timer control register.
Approx.
Min
When using the sub clock as machine clock, be sure to specify watchdog timer clock source selection bit
(carry-over signal), watchdog reset time may become longer.
(WDCS) in clock timer control register (WTC) at “0,” selecting output of clock timer.
Approx. 4.61 ms
589.82 ms
Approx.
Max
Clock cycle
2
2
2
2
/HCLK
/HCLK
/HCLK
/HCLK
14
16
18
21
2
2
2
2
11
13
15
18
Approx. 0.457 s Approx. 0.576 s
Approx. 3.584 s Approx. 4.608 s
Approx. 7.168 s Approx. 9.216 s
14.336 s
Approx.
Min
18.432 s
Approx.
Max
Clock cycle
2
2
2
/SCLK
/SCLK
/SCLK
/SCLK
2
15
16
17
12
2
2
2
2
12
13
14
9