C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 207
![DEV KIT FOR F020/F021/F022/F023](/photos/9/23/92314/c8051f020dk_sml.jpg)
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
- Current page: 207 of 272
- Download datasheet (2Mb)
20.1.2. Mode 1: 8-Bit UART, Variable Baud Rate
Mode 1 provides standard asynchronous, full duplex communication using a total of 10 bits per data byte: one start
bit, eight data bits (LSB first), and one stop bit. Data are transmitted from the TX0 pin and received at the RX0 pin.
On receive, the eight data bits are stored in SBUF0 and the stop bit goes into RB80 (SCON0.2).
Data transmission begins when an instruction writes a data byte to the SBUF0 register. The TI0 Transmit Interrupt
Flag (SCON0.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN0 Receive Enable bit (SCON0.4) is set to logic 1. After the stop bit is received, the data byte
will be loaded into the SBUF0 receive register if the following conditions are met: RI0 must be logic 0, and if SM20
is logic 1, the stop bit must be logic 1.
If these conditions are met, the eight bits of data are stored in SBUF0, the stop bit is stored in RB80 and the RI0 flag
is set. If these conditions are not met, SBUF0 and RB80 will not be loaded and the RI0 flag will not be set. An inter-
rupt will occur if enabled when either TI0 or RI0 is set.
The baud rate generated in Mode 1 is a function of timer overflow, shown in Equation 20.1 and Equation 20.2.
UART0 can use Timer 1 operating in 8-Bit Auto-Reload Mode, or Timer 2 operating in Baud Rate Generator Mode to
generate the baud rate (note that the TX and RX clocks are selected separately). On each timer overflow event (a roll-
over from all ones - (0xFF for Timer 1, 0xFFFF for Timer 2) - to zero) a clock is sent to the baud rate logic.
Timer 2 is selected as TX and/or RX baud clock source by setting the TCLK0 (T2CON.4) and/or RCLK0 (T2CON.5)
bits, respectively (see
TCLK0 or RCLK0 is set to logic 1, Timer 2 is forced into Baud Rate Generator Mode, with SYSCLK / 2 as its clock
source. If TCLK0 and/or RCLK0 is logic 0, Timer 1 acts as the baud clock source for the TX and/or RX circuits,
respectively.
The Mode 1 baud rate equations are shown below, where T1M is the Timer 1 Clock Select bit (register CKCON),
TH1 is the 8-bit reload register for Timer 1, SMOD0 is the UART0 baud rate doubler (register PCON) and
[RCAP2H , RCAP2L] is the 16-bit reload register for Timer 2.
SPACE
MARK
BIT TIMES
BIT SAMPLING
START
Section “22. TIMERS” on page 225
BIT
BaudRate
BaudRate
Figure 20.4. UART0 Mode 1 Timing Diagram
Equation 20.1. Mode 1 Baud Rate using Timer 1
Equation 20.2. Mode 1 Baud Rate using Timer 2
D0
=
=
D1
-------------------------------------------------------------------------------------------- -
32
2
------------------ -
SMOD0
32
D2
65536
Rev. 1.4
D3
–
SYSCLK 12
------------------------------------------------------- -
SYSCLK
[
for complete timer configuration details). When either
RCAP2H RCAP2L
D4
256 TH1
–
,
D5
T1M 1
C8051F020/1/2/3
–
D6
]
D7
STOP
BIT
207
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