C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 93

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

10.
The internal voltage reference circuit consists of a 1.2 V, 15 ppm/°C (typical) bandgap voltage reference generator
and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system
components or to the VREFA input pin shown in Figure 10.1. Bypass capacitors of 0.1 µF and 4.7 µF are recom-
mended from the VREF pin to AGND, as shown in Figure 10.1. See Table 10.1 for voltage reference specifications.
The VREFA pin provides a voltage reference input for ADC0 and ADC1. ADC0 may also reference the DAC0 out-
put internally, and ADC1 may reference the analog power supply voltage, via the VREF multiplexers shown in
Figure 10.1.
The Reference Control Register, REF0CN (defined in Figure 10.2) enables/disables the internal reference generator
and selects the reference inputs for ADC0 and ADC1. The BIASE bit in REF0CN enables the on-board reference
generator while the REFBE bit enables the gain-of-two buffer amplifier which drives the VREF pin. When disabled,
the supply current drawn by the bandgap and buffer amplifier falls to less than 1 µA (typical) and the output of the
buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator,
BIASE and REFBE must both be set to 1 (this includes any time a DAC is used). If the internal reference is not used,
REFBE may be set to logic 0. Note that the BIASE bit must be set to logic 1 if either ADC is used, regardless of
whether the voltage reference is derived from the on-chip reference or supplied by an off-chip source. If neither the
ADC nor the DAC are being used, both of these bits can be set to logic 0 to conserve power. Bits AD0VRS and
AD1VRS select the ADC0 and ADC1 voltage reference sources, respectively. The electrical specifications for the
Voltage Reference are given in Table 10.1.
VOLTAGE REFERENCE (C8051F021/3)
Reference
External
Voltage
Circuit
Figure 10.1. Voltage Reference Functional Block Diagram
DGND
VDD
Recommended Bypass
4.7F
R1
Capacitors
0.1F
VREFA
VREF
Rev. 1.4
REF0CN
DAC0
DAC1
Ref
REFBE
x2
AV+
1
0
0
1
C8051F020/1/2/3
Band-Gap
BIASE
1.2V
EN
ADC1
Ref
ADC0
Ref
Bias to
ADCs,
DACs
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