C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 227
![DEV KIT FOR F020/F021/F022/F023](/photos/9/23/92314/c8051f020dk_sml.jpg)
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
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22.1. Timer 0 and Timer 1
Timer 0 and Timer 1 are accessed and controlled through SFRs. Each counter/timer is implemented as a 16-bit regis-
ter accessed as two separate bytes: a low byte (TL0 or TL1) and a high byte (TH0 or TH1). The Counter/Timer Con-
trol (TCON) register is used to enable Timer 0 and Timer 1 as well as indicate their status. Both counter/timers
operate in one of four primary modes selected by setting the Mode Select bits M1-M0 in the Counter/Timer Mode
(TMOD) register. Each timer can be configured independently. Following is a detailed description of each operating
mode.
22.1.1. Mode 0: 13-bit Counter/Timer
Timer 0 and Timer 1 operate as a 13-bit counter/timer in Mode 0. The following describes the configuration and oper-
ation of Timer 0. However, both timers operate identically and Timer 1 is configured in the same manner as described
for Timer 0.
The TH0 register holds the eight MSBs of the 13-bit counter/timer. TL0 holds the five LSBs in bit positions TL0.4-
TL0.0. The three upper bits of TL0 (TL0.7-TL0.5) are indeterminate and should be masked out or ignored when read-
ing. As the 13-bit timer register increments and overflows from 0x1FFF (all ones) to 0x0000, the timer overflow flag
TF0 (TCON.5) is set and an interrupt will occur if enabled.
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. Clearing C/T selects the system clock as the input
for the timer. When C/T0 is set to logic 1, high-to-low transitions at the selected input pin (T0) increment the timer
register. (Refer to
tion on selecting and configuring external I/O pins for digital peripherals.)
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is 0 or the input signal /INT0 is
logic-level one. Setting GATE0 to logic 1 allows the timer to be controlled by the external input signal /INT0, facili-
tating pulse width measurements.
Setting TR0 does not reset the timer register. The timer register should be initialized to the desired value before
enabling the timer.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0. Timer 1
is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0.
TR0
X = Don't Care
0
1
1
1
GATE0
Section “17.1. Ports 0 through 3 and the Priority Crossbar Decoder” on page 163
X
0
1
1
/INT0
X
X
0
1
Counter/Timer
Disabled
Disabled
Enabled
Enabled
Rev. 1.4
C8051F020/1/2/3
for informa-
227
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