C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 5
![DEV KIT FOR F020/F021/F022/F023](/photos/9/23/92314/c8051f020dk_sml.jpg)
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
- Current page: 5 of 272
- Download datasheet (2Mb)
17. PORT INPUT/OUTPUT .....................................................................................................161
18. SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................183
16.1. Accessing XRAM..........................................................................................................145
16.2.Configuring the External Memory Interface .................................................................146
16.3.Port Selection and Configuration ..................................................................................146
16.4. Multiplexed and Non-multiplexed Selection.................................................................148
16.5.Memory Mode Selection ...............................................................................................150
16.6.Timing
17.1.Ports 0 through 3 and the Priority Crossbar Decoder....................................................163
17.2.Ports 4 through 7 (C8051F020/2 only)..........................................................................177
18.1.Supporting Documents ..................................................................................................184
18.2.SMBus Protocol.............................................................................................................185
16.1.1. 16-Bit MOVX Example.......................................................................................145
16.1.2. 8-Bit MOVX Example.........................................................................................145
16.4.1. Multiplexed Configuration ..................................................................................148
16.4.2. Non-multiplexed Configuration...........................................................................149
16.5.1. Internal XRAM Only ...........................................................................................150
16.5.2. Split Mode without Bank Select ..........................................................................150
16.5.3. Split Mode with Bank Select ...............................................................................151
16.5.4. External Only .......................................................................................................151
16.6.1. Non-multiplexed Mode........................................................................................153
16.6.2. Multiplexed Mode................................................................................................156
17.1.1. Crossbar Pin Assignment and Allocation ............................................................163
17.1.2. Configuring the Output Modes of the Port Pins ..................................................164
17.1.3. Configuring Port Pins as Digital Inputs ...............................................................165
17.1.4. External Interrupts (IE6 and IE7) ........................................................................165
17.1.5. Weak Pull-ups......................................................................................................165
17.1.6. Configuring Port 1 Pins as Analog Inputs (AIN1.[7:0])......................................165
17.1.7. External Memory Interface Pin Assignments ......................................................166
17.1.8. Crossbar Pin Assignment Example......................................................................168
17.2.1. Configuring Ports which are not Pinned Out.......................................................177
17.2.2. Configuring the Output Modes of the Port Pins ..................................................177
17.2.3. Configuring Port Pins as Digital Inputs ...............................................................178
17.2.4. Weak Pull-ups......................................................................................................178
17.2.5. External Memory Interface ..................................................................................178
18.2.1. Arbitration............................................................................................................185
18.2.2. Clock Low Extension...........................................................................................185
18.2.3. SCL Low Timeout ...............................................................................................186
18.2.4. SCL High (SMBus Free) Timeout.......................................................................186
16.6.1.1.16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’................................153
16.6.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’............154
16.6.1.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘110’. ..............................155
16.6.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’................................156
16.6.2.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’............157
16.6.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. ..............................158
.......................................................................................................................151
Rev. 1.4
C8051F020/1/2/3
5
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