C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 161

• Manufacturer Part Number: C8051F020-TB
• Description: BOARD PROTOTYPING W/C8051F020
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020-TB

• Contents: Board
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F020
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.
The C8051F020/1/2/3 are fully integrated mixed-signal System on a Chip MCUs with 64 digital I/O pins
(C8051F020/2) or 32 digital I/O pins (C8051F021/3), organized as 8-bit Ports. The lower ports: P0, P1, P2, and P3,
are both bit- and byte-addressable through their corresponding Port Data registers. The upper ports: P4, P5, P6, and
P7 are byte-addressable. All Port pins are 5 V-tolerant, and all support configurable Open-Drain or Push-Pull output
modes and weak pull-ups. A block diagram of the Port I/O cell is shown in Figure 17.1. Complete Electrical Specifi-
cations for the Port I/O pins are given in Table 16.1.
VDD = 2.7 V to 3.6 V, -40°C to +85°C unless otherwise specified.
Output High Voltage (V
Output Low Voltage (V
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Leakage Current
Input Capacitance
PORT-INPUT
/WEAK-PULLUP
PUSH-PULL
/PORT-OUTENABLE
PORT-OUTPUT
ANALOG INPUT
PARAMETER
PORT INPUT/OUTPUT
OL
OH
Table 17.1. Port I/O DC Electrical Characteristics
) I
Analog Select
(Port 1 Only)
) I
I
I
I
I
DGND < Port Pin < VDD, Pin Tri-state
Weak Pull-up Off
Weak Pull-up On
OH
OH
OH
OL
OL
OL
Figure 17.1. Port I/O Cell Block Diagram
= 10 µA
= 8.5 mA
= 25 mA
= -10 µA, Port I/O Push-Pull
= -3 mA, Port I/O Push-Pull
= -10 mA, Port I/O Push-Pull
CONDITIONS
Rev. 1.4
0.7 x VDD
VDD - 0.1
VDD - 0.7
DGND
VDD
MIN
C8051F020/1/2/3
VDD - 0.8
TYP
1.0
VDD
10
5
(WEAK)
MAX
VDD
0.3 x
0.1
0.6
± 1
PORT
PAD
UNITS
µA
pF
V
V
V
V
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