C8051F020-TB Silicon Laboratories Inc, C8051F020-TB Datasheet - Page 59
![BOARD PROTOTYPING W/C8051F020](/photos/28/94/289414/tqfp-100_sml.jpg)
C8051F020-TB
Manufacturer Part Number
C8051F020-TB
Description
BOARD PROTOTYPING W/C8051F020
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F020-TB
Contents
Board
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F020
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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6.
The ADC0 subsystem for the C8051F022/3 consists of a 9-channel, configurable analog multiplexer (AMUX0), a
programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approximation-register ADC with integrated
track-and-hold and Programmable Window Detector (see block diagram in Figure 6.1). The AMUX0, PGA0, Data
Conversion Modes, and Window Detector are all configurable under software control via the Special Function Regis-
ters shown in Figure 6.1. The voltage reference used by ADC0 is selected as described in
REFERENCE (C8051F020/2)” on page 91
(C8051F021/3)” on page 93
enabled only when the AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is
in low power shutdown when this bit is logic 0.
6.1.
Eight of the AMUX channels are available for external measurements while the ninth channel is internally connected
to an on-chip temperature sensor (temperature transfer function is shown in Figure 6.2). AMUX input pairs can be
programmed to operate in either differential or single-ended mode. This allows the user to select the best measure-
ment technique for each input channel, and even accommodates mode changes "on-the-fly". The AMUX defaults to
all single-ended inputs upon reset. There are two registers associated with the AMUX: the Channel Selection register
AMX0SL (Figure 6.6), and the Configuration register AMX0CF (Figure 6.7). The table in Figure 6.6 shows AMUX
functionality by channel, for each possible configuration. The PGA amplifies the AMUX output signal by an amount
determined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (Figure 6.7). The
PGA can be software-programmed for gains of 0.5, 2, 4, 8 or 16. Gain defaults to unity on reset.
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
ADC0 (10-BIT ADC, C8051F022/3 ONLY)
Analog Multiplexer and PGA
SENSOR
AGND
TEMP
AMX0CF
ADC0GTH
+
+
+
+
-
-
-
-
Figure 6.1. 10-Bit ADC0 Functional Block Diagram
AMUX
(SE or
9-to-1
DIFF)
for C8051F021/3 devices. The ADC0 subsystem (ADC0, track-and-hold and PGA0) is
AMX0SL
ADC0GTL
X
+
-
for C8051F020/2 devices, or
AV+
AD0EN
AGND
ADC0CF
ADC0LTH
Rev. 1.4
ADC
10-Bit
AV+
SAR
ADC0CN
ADC0LTL
Section “10. VOLTAGE REFERENCE
Start Conversion
10
C8051F022/3
20
Section “9. VOLTAGE
00
01
10
11
Comb.
10
Logic
AD0BUSY (W)
Timer 3 Overflow
CNVSTR
Timer 2 Overflow
AD0WINT
59
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