C8051F120-TB Silicon Laboratories Inc, C8051F120-TB Datasheet - Page 134

• Manufacturer Part Number: C8051F120-TB
• Description: BOARD PROTOTYPING W/C8051F120
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120-TB

• Contents: Board
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Kit Contents: Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
134
Bits 7
Bits 5
Bits 3
Bits 1
*Note: On the C8051F132/3, the COBANK and IFBANK bits should both remain set to the default setting of ‘01’ to
Figure 11.3. Address Memory Map for Instruction Fetches (128 kB Flash Only)
R/W
Bit7
-
–
–
–
–
6: Reserved.
4: COBANK: Constant Operations Bank Select.
2: Reserved.
0: IFBANK: Instruction Fetch Operations Bank Select.
ensure proper device functionality.
These bits select which Flash bank is targeted during constant operations (MOVC and Flash
MOVX) involving addresses 0x8000 to 0xFFFF. These bits are ignored when accessing the
Scratchpad memory areas (see
00: Constant Operations Target Bank 0 (note that Bank 0 is also mapped between 0x0000 to
0x7FFF).
01: Constant Operations Target Bank 1.
10: Constant Operations Target Bank 2.
11: Constant Operations Target Bank 3.
These bits select which Flash bank is used for instruction fetches involving addresses 0x8000 to
0xFFFF. These bits can only be changed from code in Bank 0 (see Figure 11.3).
00: Instructions Fetch From Bank 0 (note that Bank 0 is also mapped between 0x0000 to
0x7FFF).
01: Instructions Fetch From Bank 1.
10: Instructions Fetch From Bank 2.
11: Instructions Fetch From Bank 3.
SFR Definition 11.1. PSBANK: Program Space Bank Select
R/W
Bit6
-
Address
0xFFFF
0x7FFF
Internal
0x8000
0x0000
R/W
Bit5
COBANK
IFBANK = 0
Bank 0
Bank 0
R/W
Bit4
Section “15. Flash Memory” on page 199
IFBANK = 1
Bank 1
Bank 0
Rev. 1.4
R/W
Bit3
-
IFBANK = 2
Bank 2
Bank 0
R/W
Bit2
-
IFBANK = 3
Bank 3
Bank 0
R/W
Bit1
IFBANK
SFR Address:
SFR Page:
R/W
Bit0
).
0xB1
All Pages
00010001
Reset Value