C8051F120-TB Silicon Laboratories Inc, C8051F120-TB Datasheet - Page 44

• Manufacturer Part Number: C8051F120-TB
• Description: BOARD PROTOTYPING W/C8051F120
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120-TB

• Contents: Board
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Kit Contents: Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
44
AIN2.2/A10/P1.2
AIN2.3/A11/P1.3
AIN2.4/A12/P1.4
AIN2.5/A13/P1.5
AIN2.6/A14/P1.6
AIN2.7/A15/P1.7
A10m/A2/P2.2
A11m/A3/P2.3
A12m/A4/P2.4
A13m/A5/P2.5
A14m/A6/P2.6
A15m/A7/P2.7
A8m/A0/P2.0
A9m/A1/P2.1
Name
‘F120
‘F122
‘F124
‘F126
34
33
32
31
30
29
46
45
44
43
42
41
40
39
Pin Numbers
‘F121
‘F123
‘F125
‘F127
27
26
23
22
21
20
37
36
35
34
33
32
31
30
Table 4.1. Pin Definitions (Continued)
‘F130
‘F132
34
33
32
31
30
29
46
45
44
43
42
41
40
39
‘F131
‘F133
27
26
23
22
21
20
37
36
35
34
33
32
31
30
Rev. 1.4
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O Bit 8 External Memory Address bus (Multiplexed
D I/O Port 2.1. See Port Input/Output section for com-
D I/O Port 2.2. See Port Input/Output section for com-
D I/O Port 2.3. See Port Input/Output section for com-
D I/O Port 2.4. See Port Input/Output section for com-
D I/O Port 2.5. See Port Input/Output section for com-
D I/O Port 2.6. See Port Input/Output section for com-
D I/O Port 2.7. See Port Input/Output section for com-
Type
A In
A In
A In
A In
A In
A In
Port 1.2. See Port Input/Output section for com-
plete description.
Port 1.3. See Port Input/Output section for com-
plete description.
Port 1.4. See Port Input/Output section for com-
plete description.
Port 1.5. See Port Input/Output section for com-
plete description.
Port 1.6. See Port Input/Output section for com-
plete description.
Port 1.7. See Port Input/Output section for com-
plete description.
mode)
Bit 0 External Memory Address bus (Non-multi-
plexed mode)
Port 2.0
See Port Input/Output section for complete
description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.
Description