C8051F120-TB Silicon Laboratories Inc, C8051F120-TB Datasheet - Page 47

• Manufacturer Part Number: C8051F120-TB
• Description: BOARD PROTOTYPING W/C8051F120
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120-TB

• Contents: Board
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Kit Contents: Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A10m/A2/P6.2
A11m/A3/P6.3
A12m/A4/P6.4
A13m/A5/P6.5
A14m/A6/P6.6
A15m/A7/P6.7
A8m/A0/P6.0
A9m/A1/P6.1
AD0/D0/P7.0
AD1/D1/P7.1
AD2/D2/P7.2
AD3/D3/P7.3
AD4/D4/P7.4
Name
‘F120
‘F122
‘F124
‘F126
80
79
78
77
76
75
74
73
72
71
70
69
68
Pin Numbers
‘F121
‘F123
‘F125
‘F127
Table 4.1. Pin Definitions (Continued)
‘F130
‘F132
80
79
78
77
76
75
74
73
72
71
70
69
68
‘F131
‘F133
Rev. 1.4
D I/O Bit 8 External Memory Address bus (Multiplexed
D I/O Port 6.1. See Port Input/Output section for com-
D I/O Port 6.2. See Port Input/Output section for com-
D I/O Port 6.3. See Port Input/Output section for com-
D I/O Port 6.4. See Port Input/Output section for com-
D I/O Port 6.5. See Port Input/Output section for com-
D I/O Port 6.6. See Port Input/Output section for com-
D I/O Port 6.7. See Port Input/Output section for com-
D I/O Bit 0 External Memory Address/Data bus (Multi-
D I/O Port 7.1. See Port Input/Output section for com-
D I/O Port 7.2. See Port Input/Output section for com-
D I/O Port 7.3. See Port Input/Output section for com-
D I/O Port 7.4. See Port Input/Output section for com-
Type
C8051F120/1/2/3/4/5/6/7
mode)
Bit 0 External Memory Address bus (Non-multi-
plexed mode)
Port 6.0
See Port Input/Output section for complete
description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.
plete description.
plexed mode)
Bit 0 External Memory Data bus (Non-multi-
plexed mode)
Port 7.0
See Port Input/Output section for complete
description.
plete description.
plete description.
plete description.
plete description.
C8051F130/1/2/3
Description
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