MSC8144AMC-SA Freescale Semiconductor, MSC8144AMC-SA Datasheet - Page 42

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MSC8144AMC-SA

Manufacturer Part Number
MSC8144AMC-SA
Description
BOARD AMC SGL WIDTH MSC8144 DSP
Manufacturer
Freescale Semiconductor
Type
DSPr
Datasheet

Specifications of MSC8144AMC-SA

Contents
Board
For Use With/related Products
MSC8144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Electrical Characteristics
Figure 10
2.6.5
2.6.5.1
Table 24
2.6.5.2
LP-Serial links use differential signaling. This section defines terms used in the description and specification of differential
signals.
or a receiver input (RD and RD). Each signal swings between voltage levels A and B, where A > B.
Note:
42
REFCLK cycle time
Parameter Description
A
B
Figure 11
This explanation uses generic TD/TD/RD/RD signal names. These correspond to SRIO_TXD/SRIO_TXD/
SRIO_RXD/SRIO_RXD respectively.
lists AC signal specifications.
provides the AC test load for the DDR bus.
Serial RapidIO Timing and SGMII Timing
AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK
Signal Definitions
shows how the signals are defined. The figure shows waveforms for either a transmitter output (TD and TD)
Table 24. SDn_REF_CLK and SDn_REF_CLK AC Signal Specifications
Output
TD or RD
TD or RD
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Symbol
t
Figure 11. Differential V
REF
Z
Min
0
Figure 10. DDR AC Test Load
= 50 Ω
Differential Peak-Peak = 2 × (A – B)
10 (8, 6.4)
Typical
PP
of Transmitter or Receiver
Max
R
L
= 50 Ω
Units
ns
8 ns applies only to serial RapidIO system
with 125-MHz reference clock. 6.4 ns
applies only to serial RapidIO systems with
a 156.25 MHz reference clock.
Note:
V
DDDDR
SGMII uses the 8 ns (125 MHz)
value only.
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Comments
Freescale Semiconductor

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