AD9777-EB Analog Devices Inc, AD9777-EB Datasheet - Page 31

• Manufacturer Part Number: AD9777-EB
• Description: BOARD EVAL FOR AD9777
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9777-EB

• Rohs Status: RoHS non-compliant
• Number Of Dac's: 2
• Number Of Bits: 16
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 160M
• Data Interface: Parallel
• Settling Time: 11ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9777

The selection of the data for the I or Q channel is determined by
the state of the logic level at Pin 31 (IQSEL when the AD9777 is
in one-port mode) on the rising edge of ONEPORTCLK.
Under these conditions, IQSEL = 0 latches the data into the I
channel on the clock rising edge, while IQSEL = 1 latches the
data into the Q channel. It is possible to invert the I and Q
selection by setting Control Register 02h, Bit 1 to the invert
state (Logic 1). Figure 54 illustrates the timing requirements for
the data inputs as well as the IQSEL input. Note that the 1×
interpolation rate is not available in one-port mode.
The DAC output sample rate in one-port mode is equal to
CLKIN multiplied by the interpolation rate. If zero stuffing is
used, another factor of 2 must be included to calculate the DAC
sample rate.
ONEPORTCLK INVERSION
(Control Register 02h, Bit 2)
By programming this bit, the ONEPORTCLK signal shown in
Figure 54 can be inverted. With inversion enabled, t
the delay between the rising edge of the external clock and the
falling edge of ONEPORTCLK. The setup and hold times, t
and t
There is no other effect on timing.
ONEPORTCLK DRIVER STRENGTH
The drive capability of ONEPORTCLK is identical to that of
DATACLK in the two-port mode. Refer to Figure 53 for
performance under load conditions.
INPUT DATA AT PORT 1
I AND Q INTERLEAVED
H
, are with respect to the falling edge of ONEPORTCLK.
ONEPORTCLK
CLKIN
IQSEL
Figure 54. Timing Requirements in One-Port
Input Mode, with the PLL Enabled
t
IQS
t
OD
t
S
t
H
t
IQH
t
t
t
t
t
OD
S
H
IQS
IQH
= 3.0ns (MAX)
= –0.5ns (MAX)
= 4.0ns (MIN)
= 3.5ns (MAX)
= –1.5ns (MAX
TO 5.5ns (MAX)
OD
refers to
S
Rev. C | Page 31 of 60
IQ PAIRING
(Control Register 02h, Bit 0)
In one-port mode, the interleaved data is latched into the
AD9777 internal I and Q channels in pairs. The order of how
the pairs are latched internally is defined by this control register.
The following is an example of the effect this has on incoming
interleaved data.
Given the following interleaved data stream, where the data
indicates the value with respect to full scale:
I
0.5
With the control register set to 0 (I first), the data appears at the
internal channel inputs in the following order in time:
I Channel
Q Channel
With the control register set to 1 (Q first), the data appears at
the internal channel inputs in the following order in time:
I Channel
Q Channel
The values x and y represent the next I value and the previous Q
value in the series.
PLL DISABLED, TWO-PORT MODE
With the PLL disabled, a clock at the DAC output rate must be
applied to CLKIN. Internal clock dividers in the AD9777 syn-
thesize the DATACLK signal at Pin 8, which runs at the input
data rate and can be used to synchronize the input data. Data is
latched into input Port 1 and Port 2 of the AD9777 on the rising
edge of DATACLK. DATACLK speed is defined as the speed of
CLKIN divided by the interpolation rate. With zero stuffing en-
abled, this division increases by a factor of 2. Figure 55 illustrates
the delay between the rising edge of CLKIN and the rising edge
of DATACLK, as well as t
The programmable modes DATACLK inversion and DATACLK
driver strength described in the PLL Enabled, Two-Port Mode
section have identical functionality with the PLL disabled.
The data rate CLK created by dividing down the DAC clock in
this mode can be programmed (via Register x03h, Bit 7) to be
output from the SPI_SDO pin, rather than the DATACLK pin.
In some applications, this may improve complex image rejec-
tion. t
clock out.
OD
Q
0.5
increases by 1.6 ns when SPI_SDO is used as data rate
I
1
Q
1
0.5
y
0.5
0.5
S
I
0.5
and t
1
0.5
H
1
1
in this mode.
Q
0.5
0.5
1
I
0
0.5
0.5
0
0.5
Q
0
AD9777
I
0.5
0
0
0.5
0
Q
0.5
0.5
0.5
x
0.5