EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 12

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADuC7019/20/21/22/24/25/26/27/28
Table 6. SPI Master Mode Timing (PHASE Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider or CD bits in PLLCON MMR. t
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
SCLOCK
SCLOCK
MOSI
MISO
1
t
1
DAV
t
SH
Figure 6. SPI Master Mode Timing (PHASE Mode = 1)
t
DSU
HCLK
MSB IN
= t
t
DHD
UCLK
2
MSB
t
SL
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2
CD
.
t
DF
t
DR
BITS 6 TO 1
BITS 6 TO 1
Min
1 × t
2 × t
UCLK
UCLK
t
SR
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
LSB IN
t
SF
LSB
HCLK
HCLK
25
12.5
12.5
12.5
Max
12.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns