EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 74

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADuC7019/20/21/22/24/25/26/27/28
PLAADC Register
Name
PLAADC
PLAADC is the PLA source for the ADC start conversion signal.
Table 70. PLAADC MMR Bit Descriptions
Bit
31:5
4
3:0
PLADIN Register
Name
PLADIN
PLADIN is a data input MMR for PLA.
Value
0000
0001
1111
Address
0xFFFF0B48
Address
0xFFFF0B4C
Description
Reserved.
ADC Start Conversion Enable Bit. Set by user
to enable ADC start conversion from PLA.
Cleared by user to disable ADC start
conversion from PLA.
ADC Start Conversion Source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Default Value
0x00000000
Default Value
0x00000000
Access
R/W
Access
R/W
Rev. B | Page 74 of 92
Table 71. PLADIN MMR Bit Descriptions
Bit
31:16
15:0
PLADOUT Register
Name
PLADOUT
PLADOUT is a data output MMR for PLA. This register is
always updated.
Table 72. PLADOUT MMR Bit Descriptions
Bit
31:16
15:0
PLALCK Register
Name
PLALCK
PLALCK is a PLA lock option. Bit 0 is written only once. When
set, it does not allow modifying any of the PLA MMRs, except
PLADIN. A PLA tool is provided in the development system to
easily configure the PLA.
Description
Reserved.
Output Bit from Element 15 to Element 0.
Address
0xFFFF0B50
Address
0xFFFF0B54
Description
Reserved.
Input Bit to Element 15 to Element 0.
Default Value
0x00000000
Default Value
0x00
Access
R
Access
W