EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 57

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Both switching edges are moved by an equal amount
(PWMDAT1 × t
patterns.
Also shown is the PWMSYNC pulse and Bit 0 of the PWMSTA
register, which indicates whether operation is in the first or
second half cycle of the PWM period.
The resulting on-times of the PWM signals over the full PWM
period (two half periods) produced by the timing unit can be
written as follows:
On the high side
and the corresponding duty cycles (d)
and on the low side
and the corresponding duty cycles (d)
The minimum permissible t
corresponding to a 0% duty cycle. In a similar fashion, the
maximum value is t
Figure 59 shows the output signals from the timing unit for
operation in double update mode. It illustrates a general case
where the switching frequency, dead time, and duty cycle are all
changed in the second half of the PWM period. The same value
for any or all of these quantities can be used in both halves of the
PWM cycle. However, there is no guarantee that symmetrical
PWM signals are produced by the timing unit in double update
mode. Figure 59 also shows that the dead time inserted into the
PWM signals are done so in the same way as demonstrated in
single update mode.
PWMSTA (0)
PWMSYNC
t
t
d
t
t
d
0HH
0HL
0LH
0LL
0H
OL
Figure 59. Typical PWM Outputs of the 3-Phase Timing Unit
–PWMDAT0
= t
= PWMDAT0 + 2(PWMCH0 + PWMDAT1)
= t
= PWMDAT0 − 2(PWMCH0 − PWMDAT1) × t
= PWMDAT0 − 2(PWMCH0 + PWMDAT1)
0H
= PWMDAT0 + 2(PWMCH0 − PWMDAT1) × t
0L
0LH
0HH
2 × PWMDAT1
/t
PWMCH0
/t
S
S
= ½ − (PWMCH0 + PWMDAT1)/PWMDAT0
CORE
= ½ + (PWMCH0 − PWMDAT1)/PWMDAT0
1
/2
S
PWMDAT0
) to preserve the symmetrical output
, corresponding to a 100% duty cycle.
1
1
(Double Update Mode)
PWMDAT2
0
1
0H
and t
1
–PWMDAT0
+PWMDAT0
+1
0L
values are zero,
2
1
/2
/2
PWMDAT0
PWMDAT2
0
2 × PWMDAT1
PWMCH0
2
+PWMDAT0
2
+1
× t
× t
2
CORE
CORE
CORE
CORE
2
Rev. B | Page 57 of 92
2
/2
In general, the on-times of the PWM signals in double update
mode can be defined as follows:
On the high side
where the subscript 1 refers to the value of that register during
the first half cycle, and the subscript 2 refers to the value during
the second half cycle.
The corresponding duty cycles (d) are
On the low side
where the subscript 1 refers to the value of that register during
the first half cycle, and the subscript 2 refers to the value during
the second half cycle.
The corresponding duty cycles (d) are
For the completely general case in double update mode
(see Figure 59), the switching period is given by
Again, the values of t
zero and t
PWM signals similar to those illustrated in Figure 58 and
Figure 59 can be produced on the 1H, 1L, 2H, and 2L outputs by
programming the PWMCH1 and PWMCH2 registers in a manner
identical to that described for PWMCH0. The PWM controller
does not produce any PWM outputs until all of the PWMDAT0,
PWMCH0, PWMCH1, and PWMCH2 registers have been written
to at least once. Once these registers have been written, internal
counting of the timers in the 3-phase timing unit is enabled.
Writing to the PWMDAT0 register starts the internal timing of
the main PWM timer. Provided that the PWMDAT0 register is
written to prior to the PWMCH0, PWMCH1, and PWMCH2
registers in the initialization, the first PWMSYNC pulse and
interrupt (if enabled) appear 1.5 × t
after the initial write to the PWMDAT0 register in single update
mode. In double update mode, the first PWMSYNC pulse
appears after PWMDAT0 × t
t
PWMCH0
t
PWMCH0
d
PWMCH0
(PWMDAT0
t
PWMCH0
t
PWMCH0
d
PWMCH0
PWMDAT1
t
0HH
0HL
0LH
0LL
S
ADuC7019/20/21/22/24/25/26/27/28
0H
0L
=
= t
= t
= (PWMDAT0
= (PWMDAT0
= (PWMDAT0
(PWMDAT0
= (PWMDAT0
S
.
0LH
0HH
/t
/t
S
2
2
1
2
2
1
S
= (PWMDAT0
− PWMDAT1
+ PWMDAT1
+ PWMCH0
+ PWMDAT1
− PWMDAT1
+ PWMCH0
= (PWMDAT0
2
)/(PWMDAT0
1
+ PWMDAT0
0H
1
1
+ PWMDAT0
and t
1
1
/2
1
/2
/2
/2
+ PWMDAT0
+ PWMDAT0
+ PWMDAT0
+ PWMDAT0
0L
CORE
2
2
− PWMDAT1
+ PWMDAT1
are constrained to lie between
1
1
1
1
1
1
− PWMDAT1
+ PWMDAT1
+ PWMDAT1
− PWMDAT1
/2 + PWMDAT0
1
/2
seconds.
2
+ PWMDAT0
)
+ PWMDAT0
CORE
2
) × t
× PWMDAT0 seconds
2
2
2
/2
2
/2
/2
CORE
/2
− PWMCH0
− PWMCH0
1
1
+ PWMCH0
+ PWMCH0
− PWMDAT1
+
2
2
2
2
) × t
) × t
) × t
) × t
2
)
2
2
/2 +
/2
CORE
CORE
CORE
CORE
+
1
1
1
1
−
−
+
+
2
)/