EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 68

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADuC7019/20/21/22/24/25/26/27/28
I
The ADuC7019/20/21/22/24/25/26/27/28 support two licensed I
interfaces. The I
master and a full slave interface. Because the two I
identical, this data sheet describes only I2C0 in detail. Note that the
two masters and one of the slaves have individual interrupts (see
the Interrupt System section).
Note that when configured as an I
ADuC7019/20/21/22/24/25/26/27/28 cannot generate a
repeated start condition.
The two pins used for data transfer, SDA and SCL, are configured
in a wired-AND format that allows arbitration in a multimaster
system. These pins require external pull-up resistors. Typical
pull-up values are 10 kΩ.
The I
programmed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer during the initial address
transfer. If the master does not lose arbitration and the slave
acknowledges, the data transfer is initiated. This continues until
the master issues a stop condition and the bus becomes idle.
The I
any given time. The same I
support master and slave modes.
Serial Clock Generation
The I
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2C0DIV MMR as follows:
where:
f
DIVH = the high period of the clock.
DIVL = the low period of the clock.
Thus, for 100 kHz operation,
and for 400 kHz,
The I2CxDIV register corresponds to DIVH:DIVL.
UCLK
2
C-COMPATIBLE INTERFACES
DIVH = DIVL = 0xCF
DIVH = 0x28, DIVL = 0x3C
= clock before the clock divider.
2
2
2
f
C peripheral can only be configured as a master or slave at
C master in the system generates the serial clock for a
C bus peripheral’s address in the I
SERIAL
CLOCK
2
C interfaces are both implemented as a hardware
=
2 (
+
DIVH
2
C channel cannot simultaneously
2
C system consists of a master
f
UCLK
)
+
(2
2
C master device, the
+
DIVL
2
C bus system is
)
2
C interfaces are
Rev. B | Page 68 of 92
2
C
Slave Addresses
The registers I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3 contain
the device IDs. The device compares the four I2C0IDx registers
to the address byte. To be correctly addressed, the 7 MSBs of either
ID register must be identical to that of the 7 MSBs of the first
received address byte. The LSB of the ID registers (the transfer
direction bit) is ignored in the process of address recognition.
I
The I
discussed in this section.
I2CxMSTA Registers
Name
I2C0MSTA
I2C1MSTA
I2CxMSTA are status registers for the master channel.
Table 61. I2C0MSTA MMR Bit Descriptions
Bit
7
6
5
4
3
2
1
0
I2CxSSTA Registers
Name
I2C0SSTA
I2C1SSTA
I2CxSSTA are status registers for the slave channel.
2
C Registers
2
C peripheral interface consists of 18 MMRs, which are
Access
Type
R/W
R
R
R
R
R
R
R
Address
0xFFFF0800
0xFFFF0900
Address
0xFFFF0804
0xFFFF0904
Description
Master Transmit FIFO Flush. Set by user to flush
the master Tx FIFO. Cleared automatically once
the master Tx FIFO is flushed. This bit also
flushes the slave receive FIFO.
Master Busy. Set automatically if the master is
busy. Cleared automatically.
Arbitration Loss. Set in multimaster mode if
another master has the bus. Cleared when the
bus becomes available.
No ACK. Set automatically if there is no
acknowledge of the address by the slave
device. Cleared automatically by reading the
I2C0MSTA register.
Master Receive IRQ. Set after receiving data.
Cleared automatically by reading the I2C0MRX
register.
Master Transmit IRQ. Set at the end of a
transmission. Cleared automatically by writing
to the I2C0MTX register.
Master Transmit FIFO Underflow. Set
automatically if the master transmit FIFO is
underflowing. Cleared automatically by writing
to the I2C0MTX register.
Master TX FIFO Not Full. Set automatically if the
slave transmit FIFO is not full. Cleared automati-
cally by writing twice to the I2C0STX register.
Default Value
0x00
0x00
Default Value
0x01
0x01
Access
R/W
R/W
Access
R
R