M5271EVB Freescale Semiconductor, M5271EVB Datasheet - Page 9

• Manufacturer Part Number: M5271EVB
• Description: BOARD EVAL FOR MCF5270/71
• Manufacturer: Freescale Semiconductor

Specifications of M5271EVB

• Processor To Be Evaluated: MCF5271
• Interface Type: RS-232, Ethernet
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

5.2.1
Figure 2
OV
5.2.1.1
If OV
connected to the OV
up before V
power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the
power supplies should be slower than 1 μs to avoid turning on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
5.2.1.2
If V
impedance state. There is no limit on how long after V
down. V
Freescale Semiconductor
DD
1. Use 1 ms or slower rise time for all supplies.
2. V
DD
DD
is specified relative to V
OV
voltage regulator.
is powered down first, then sense circuits in the I/O pads cause all output drivers to be in a high
DD
shows situations in sequencing the I/O V
is powered up with V
DD
DD
DD
Supply Voltage Sequencing and Separation Cautions
should not lag OV
and OV
Power Up Sequence
Power Down Sequence
going to the higher external voltages. One way to accomplish this is to use a low drop-out
must power up. V
3.3V
2.5V
1.5V
DD
DD
Notes:
0
Figure 2. Supply Voltage Sequencing and Separation Cautions
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 4
1.
2.
3.
4.
/V
to be in a high impedance state. There is no limit on how long after OV
VDD should not exceed OVDD or VDDPLL by more than 0.4 V
at any time, including power-up.
Recommended that VDD should track OVDD/VDDPLL up to
0.9 V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (OVDD,
VDD, or VDDPLL) by more than 0.5 V at any time, including during power-up.
Use 1 ms or slower rise time for all supplies.
DDPLL
DD
1
DD
DD
should track up to 0.9 V, then separate for the completion of ramps with
DD
at 0 V, then the sense circuits in the I/O pads cause all pad output drivers
or V
.
2
should not lead the OV
DDPLL
Supplies Stable
going low by more than 0.4 V during power down or there
DD
(OV
DD
powers down before OV
DD
), PLL V
DD
or V
DDPLL
DD
(V
OV
V
DD
DDPLL
by more than 0.4 V during
DD,
V
DDPLL
DD
), and Core V
Design Recommendations
Time
/V
DDPLL
must power
DD
DD
powers
(V
DD
).
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