HS7705KCM01H Renesas Electronics America, HS7705KCM01H Datasheet - Page 241

• Manufacturer Part Number: HS7705KCM01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7705KCM01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6.12 Measurement Item (cont)
Selected Name
Cacheable area access cycle
Cacheable area instruction access cycle
Cacheable area data access cycle
Access counts other than instruction/data
Non-cacheable area access counts
Non-cacheable area instruction access counts
Non-cacheable area data access counts
Cacheable area access counts
Cacheable area instruction access counts
Cacheable area data access counts
Each measurement condition is also counted when conditions in table 6.13 are generated.
Table 6.13 Performance Measurement Conditions to be Counted
Measurement Condition
No caching due to the
settings of TLB cacheable
bit
Cache-on counting
Branch count
Notes: 1. In the non realtime trace mode of the AUD trace, normal counting cannot be
2. Since the clock source of the counter is the CPU clock, counting also stops when the
performed because the generation state of the stall or the execution cycle is changed.
clock halts in the sleep mode.
Counted for accessing the cacheable area.
Accessing the non-cacheable area is counted less than the actual
number of cycles and counts. Accessing the cacheable area is
counted more than the actual number of cycles and counts.
are valid for one branch.
Notes
The counter value is incremented by 2. This means that two cycles
Option
CC
CDC
NAM
NCIN
NCDN
CIN
CDN
CIC
NCN
CN
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