HS7750KCI01H Renesas Electronics America, HS7750KCI01H Datasheet - Page 31

• Manufacturer Part Number: HS7750KCI01H
• Description: ON CHIP DEBUG EMULATOR
• Manufacturer: Renesas Electronics America

Specifications of HS7750KCI01H

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 2.9 Performance Count Conditions
Event
All count conditions
Instruction cache miss
count
TLB miss count
Instruction fetch count
Instruction issue count
FPU instruction issue
count
(c) Counting method
One of the following methods can be specified by each of measurement channels 1 and 2.
1.
2.
When the above method 1 is specified, one CPU operating clock cycle is counted as one.
When method 2 is specified, the count is incremented by 3, 4, 6, 8, 12, or 24, according to the
clock frequency ratio (ratio of the CPU clock to the bus clock). In this case, the execution time
can be calculated by the following expression:
Counted by the CPU operating clock
Counted by the ratio of the CPU operating clock to the bus clock
Count Condition
When the event to be counted up is canceled by an
exception.
When the TLB miss is canceled by an exception
having a higher priority than that of the TLB miss
Counts one when two instructions are issued at the
same time.
Counts one to three when instruction fetch
exception (instruction address error, instruction
TLB miss exception, or instruction TLB protection
violation exception) occurs.
LDS Rm, FPUL, LDS.L @Rm+, FPUL, LDS Rm,
FPSCR, LDS.L @Rm+, FPSCR,
STS FPUL, Rn, STS.L FPUL, @-Rn, STS FPSCR,
Rn, STS.L FPSCR, @-Rn
Others: instructions that the instruction code is
H'Fxxx
Includes instruction fetch for the cache-off area
to count the number of times the instruction has
not been fetched in one cycle.
When a cache miss occurs during an overrun
fetch generated at exception.
When the instruction fetch request by the CPU
is accepted.
Does not count when the cache is bypassed
from the external bus to supply the instruction
to the CPU at instruction cache miss.
Counts one when two instructions are issued at
the same time.
The following shows the FPU instructions:
Target Mode
All
EC
DT and ET
EF and EA
E
E and E2
EFP
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