HS7760KCI02H Renesas Electronics America, HS7760KCI02H Datasheet - Page 244

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HS7760KCI02H

Manufacturer Part Number
HS7760KCI02H
Description
ON CHIP DEBUG EMULATOR W/TRACE
Manufacturer
Renesas Electronics America
Datasheets

Specifications of HS7760KCI02H

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 6.12 Measurement Conditions (cont)
Measurement Condition Mode
Instruction execution
count
Interrupt count
UBC satisfaction count
Cache fill cycle count
Elapsed time count
Pipeline freeze cycle count PFCF
Note: The non-cache operand accesses due to the PREF instruction or TLB.c=0 do not count up.
218
E
E2
EFP
ETR
INT
NMI
UA
UB
ECF
OCF
TM
PFCD
PFB
Description
The number of times instructions are issued.
The number of times two instructions are issued at the
same time.
The number of times FPU instructions are issued.
The number of times the TRAPA instruction is executed.
The number of interrupts except NMI.
The number of NMI interrupts.
The number of times channel A of the UBC is satisfied.
The number of times channel B of the UBC is satisfied.
The number of instruction cache fill cycles.
The number of operand cache fill cycles.
The number of cycles for elapsed time.
Pipeline freeze cycle due to instruction cache misses.
Pipeline freeze cycle due to operand cache misses.
Pipeline freeze cycle due to branch instructions or
exceptions.

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