DK-PCI-2C35N Altera, DK-PCI-2C35N Datasheet - Page 29

• Manufacturer Part Number: DK-PCI-2C35N
• Description: PCI KIT W/CYCLONE II EP2C35N
• Manufacturer: Altera
• Series: Cyclone® IIr
• Type: FPGA: PCI Development Kitr

Specifications of DK-PCI-2C35N

• Contents: Dev Board, Quartus®II Web Edition, Cables, Accessories, Reference Designs and Demos
• For Use With/related Products: Cyclone ll 2C35N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1733

Altera Corporation
May 2005
cpd_top.vhd
vhdl_components.vhd —
pci_top.vhd
backend.vhd
Table 2–2. Prototyping Walkthrough Reference Design Source Files (Part 1 of 2)
File
f
—
pci_mt64
pci_local
Subdirectory
Refer to
on page 2–6
To simulate your design using this walkthrough, you need the Model
Technology ModelSim simulator version 6.0 or later, which is not
included with the kit.
1
Prototyping Walkthrough Files
The prototyping walkthrough uses reference design source files,
simulation files, and compilation files that you copy from the PCI
Development Kit, Cyclone II Edition CD-ROM installation directory to your
working directory.
Table 2–2
walkthrough. These files are located in the <path>\cycloneii_pci_kit-
v1.0.0\reference_design\vhdl directory.
(1)
PCI Development Kit, Cyclone II Edition Getting Started User Guide
“Software Installation” on page 2–4
The reference design’s DDR2 memory simulation model is only
available in Verilog HDL, and the reference design is in VHDL.
Mixed VHDL and Verilog HDL simulation may require
additional ModelSim licenses.
describes the reference design source files used in the
The top-level file that instantiates the PCI and DDR2 SDRAM cores
and the local design. Refer to AN 390: PCI-to-DDR2 SDRAM
Reference Design for a description of the local design.
The VHDL component instantiation templates.
This wrapper file implements the pci_mt64 core. The file was
generated with the PCI Compiler wizard and the following settings:
●
●
●
●
●
●
●
●
●
For more information, refer to the PCI Compiler User Guide.
The top level of the local PCI interface.
for more information.
VHDL output file
64-bit master/target MegaCore function (pci_mt64)
Device ID is set to 0x0009
Revision ID is set to 0x1
Subsystem ID is set to 0xE102
Subsys Vendor ID is set to 0x1172
BAR0 is a 1-MByte memory
BAR1 is a 64-MByte prefetchable memory
All other parameters are at the default values
Core Version a.b.c variable
Description
and
“Setting Up Licensing”
Getting Started
2–19