DK-PCI-2C35N Altera, DK-PCI-2C35N Datasheet - Page 38

• Manufacturer Part Number: DK-PCI-2C35N
• Description: PCI KIT W/CYCLONE II EP2C35N
• Manufacturer: Altera
• Series: Cyclone® IIr
• Type: FPGA: PCI Development Kitr

Specifications of DK-PCI-2C35N

• Contents: Dev Board, Quartus®II Web Edition, Cables, Accessories, Reference Designs and Demos
• For Use With/related Products: Cyclone ll 2C35N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1733

Using the Board as a Prototyping Platform
2–28
PCI Development Kit, Cyclone II Edition Getting Started User Guide
1
For this walkthrough, the steps are omitted and you use the provided
ready-to-use constraint files cpd_top.qsf in the
c:\ pci_prototype_example\QuartusII directory.
9.
10. Choose Compilation Report (Processing menu) and expand the
11. Choose Compilation Report (Processing menu) and select Pin-Out
Configure Your Cyclone II Device
You can configure the Cyclone II device using either the SOF or POF
created in the previous section via the JTAG interface or by programming
the on-board serial flash memory. Follow the steps outlined in
“Configuring the Cyclone II Device” on page
preferred configuration method. The next step in this walkthrough
assumes that you have programmed your POF into the serial flash
memory and you are ready to test your new configuration in hardware.
1
Choose Start Compilation (Processing menu) to synthesize and
compile the project and generate the cpd_top.sof and cdp_top.pof
files.
If you do not have licenses for the pci_mt64 MegaCore function or
the DDR & DDR2 SDRAM Controller Compiler, you will not be able
to generate unrestricted programming files. In this case, use the file
cpd_top.pof from your working directory to complete the steps in
this walkthrough.
Timing Analyzer section to check the timing of your compiled
design.
File to make sure all of your pins are assigned properly.
To ensure that the prototype pin assignments match the board’s
pin assignments, you should use the provided constraint file
(cpd_top.qsf) for pin-out reference. Unless otherwise indicated,
you should assume that constraint files not shipped with the kit
contain different pin assignments from that required by the
board.
Core Version a.b.c variable
The kit’s constraint file (.qsf) is made for the PCI Compiler
version 4.0.0 and the DDR & DDR2 SDRAM Controller
Compiler version 3.2.0 using the Quartus II software
version 5.0; therefore, the constraint files should be used
with the same MegaCore function and software versions. If
you use a different MegaCore function or software version,
you may experience timing violations or compilation
errors.
2–15, depending on your
Altera Corporation
May 2005