MPC5553EVB Freescale Semiconductor, MPC5553EVB Datasheet - Page 45

• Manufacturer Part Number: MPC5553EVB
• Description: KIT EVAL MPC5553MZP132
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC5553EVB

• Contents: Eval Board and Demo Software
• Processor To Be Evaluated: MPC55xx
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MPC5553
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.14
Media Independent Interface (MII) Fast Ethernet Controller (FEC) signals use transistor-to-transistor logic
(TTL) signal levels compatible with devices operating at 3.3 V. The timing specifications for the MII FEC
signals are independent of the system clock frequency (part speed designation).
3.14.1
The receive functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz plus one percent.
There is no minimum frequency requirement. The processor clock frequency must exceed four times the
FEC_RX_CLK frequency.
Table 28
Figure 28
Freescale Semiconductor
Spec
1
2
3
4
FEC_RXD[3:0] (inputs)
FEC_RX_CLK (input)
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold
FEC_RX_CLK pulse-width high
FEC_RX_CLK pulse-width low
lists MII FEC receive channel timings.
Fast Ethernet AC Timing Specifications
shows MII FEC receive signal timings listed in
MII FEC Receive Signal Timing
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and FEC_RX_CLK
FEC_RX_ER
FEC_RX_DV
Figure 28. MII FEC Receive Signal Timing Diagram
Characteristic
MPC5553 Microcontroller Data Sheet, Rev. 3.0
Table 28. MII FEC Receive Signal Timing
1
2
3
Table
28.
4
Min.
35%
35%
5
5
65%
65%
Max
—
—
Electrical Characteristics
FEC_RX_CLK period
FEC_RX_CLK period
Unit
ns
ns
45