MPC5553EVB Freescale Semiconductor, MPC5553EVB Datasheet - Page 61

• Manufacturer Part Number: MPC5553EVB
• Description: KIT EVAL MPC5553MZP132
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC5553EVB

• Contents: Eval Board and Demo Software
• Processor To Be Evaluated: MPC55xx
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MPC5553
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Section 3.7.1, “Input Value of Pins During POR Dependent on
Location
From:
Added the following text directly before this section and after
Power-on Sequence:
To:
‘When powering the device, V
‘To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as ones
V
internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state
when POR negates. V
the V
requirements when powering down.’
‘The values in
power up.
Before exiting the internal POR state, the voltage on the pins goes to high-impedance until POR negates. When
the internal POR negates, the functional state of the signal during reset applies and the weak pull devices (up or
down) are enabled as defined in the device Reference Manual. If V
signals, the weak-pull devices can pull the signals to V
To avoid this condition, minimize the ramp time of the V
enable the external circuitry connected to the device outputs.’
(1s) when POR negates, V
device by more than the V
RESET power pin (V
V
applies during power up. V
DD33
DDEH6
Table 32. Global and Text Changes Between Rev. 2.0 and 3.0 (continued)
DD33
lag specification listed in
supplies, but cannot lag both by more than the V
lag specification. This V
Table 7
DDEH6
DD33
and
MPC5553 Microcontroller Data Sheet, Rev. 3.0
DD33
Table 8
DD33
DD33
) by more than the V
can lag V
DD33
lag specification in
Table
has no lead or lag requirements when powering down.’
must not lag V
DD33
do not include the effect of the weak pull devices on the output pins during
must not lag V
DDSYN
6. This avoids accidentally selecting the bypass clock mode because the
lag specification only applies during power up. V
Description of Change
or the RESET power pin (V
DDSYN
VDD33,” changed:
DD33
DDSYN
Table
lag specification. V
and the RESET pin power (V
DDE
DD
DD33
and the RESET power pin (V
6. V
Table 8
supply to a time period less than the time required to
and V
DD33
lag specification. This V
Revision History for the MPC5553 Data Sheet
DDEH
Pin Status for Medium / Slow Pads During the
individually can lag either V
DD
is too low to correctly propagate the logic
DDEH6
.
DD33
), but cannot lag both by more than
can lag one of the V
DDEH6
DD33
DDEH6
DD33
) when powering the
lag specification only
) by more than the
has no lead or lag
DDSYN
DDSYN
or the
or
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