EVAL-ADT7467EBZ ON Semiconductor, EVAL-ADT7467EBZ Datasheet - Page 23

• Manufacturer Part Number: EVAL-ADT7467EBZ
• Description: BOARD EVALUATION FOR ADT7467
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of EVAL-ADT7467EBZ

• Sensor Type: Temperature
• Sensing Range: -40°C ~ 120°C
• Interface: SMBus (2-Wire/I²C)
• Sensitivity: ±1.5°C
• Voltage - Supply: 3 V ~ 5.5 V
• Embedded: No
• Utilized Ic / Part: ADT7467
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.
5.
6.
7.
Masking Interrupt Sources
Interrupt Mask Registers 1 and 2 are located at Address 0x74
and Address 0x75, respectively, and allow individual interrupt
sources to be masked to prevent SMBALERT interrupts. Note
that masking an interrupt source prevents only the SMBALERT
output from being asserted; the appropriate status bit is set
normally.
Interrupt Mask Register 1 (0x74)
Bit 7 (OOL) = 1 masks SMBALERT for any alert condition
flagged in Interrupt Status Register 2.
Bit 6 (R2T) = 1 masks SMBALERT for Remote 2 temperature
channel.
Bit 5 (LT) = 1 masks SMBALERT for local temperature channel.
Bit 4 (R1T) = 1 masks SMBALERT for Remote 1 temperature
channel.
Bit 2 (V
Bit 0 (V
Interrupt Mask Register 2 (0x75)
Bit 7 (D2) = 1 masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1 masks SMBALERT for Diode 1 errors.
Bit 5 (F4P) = 1 masks SMBALERT for Fan 4 failure.
If the TACH4 pin is used as the THERM input, this bit masks
SMBALERT for a THERM event.
STATUS BIT
HIGH LIMIT
TEMPERATURE
SMBALERT
“STICKY”
Figure 29. Effect of Masking the Interrupt Source on SMBALERT Output
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Register 0x74 and
Register 0x75).
Take the appropriate action for a given interrupt source.
Exit the interrupt handler.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 29.
CC
CCP
) = 1 masks SMBALERT for V
) = 1 masks SMBALERT for V
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
CC
CCP
(TEMP BELOW LIMIT)
channel.
CLEARED ON READ
(SMBALERT REARMED)
INTERRUPT MASK BIT
channel.
CLEARED
Rev. 3 | Page 23 of 77 | www.onsemi.com
Bit 4 (FAN3) = 1 masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1 masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1 masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1 masks SMBALERT for overtemperature
(exceeding THERM temperature limits).
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default. Pin 5
or Pin 9 can be reconfigured as an SMBALERT output to signal
out-of-limit conditions.
Table 12. Configuring Pin 5 as SMBALERT Output
Register
Configuration Register 3 (0x78)
Assigning THERM Functionality to a Pin
Pin 9 on the ADT7467 has four possible functions: SMBALERT,
THERM, GPIO, and TACH4. The user chooses the required
functionality by setting Bit 0 and Bit 1 of Configuration Register 4
at Address 0x7D.
Table 13. Configuring Pin 9
Bit 1
0
0
1
1
Once Pin 9 is configured as THERM, it must be enabled (Bit 1,
Configuration Register 3 at Address 0x78).
THERM as an Input
When THERM is configured as an input, the user can time
assertions on the THERM pin. This can be useful for connect-
ing to the PROCHOT output of a CPU to gauge system
performance.
The user can also set up the ADT7467 so that when the THERM
pin is driven low externally, the fans run at 100%. The fans run
at 100% for the duration of the time that the THERM pin is
pulled low. This is done by setting the BOOST bit (Bit 2) in
Configuration Register 3 (0x78) to 1. This only works if the fan
is already running, for example, in manual mode when the
current duty cycle is above 0x00, or in automatic mode when
the temperature is above T
or if the duty cycle in manual mode is set to 0x00, externally
pulling THERM low has no effect. See Figure 30 for more
information.
Bit 0
0
1
0
1
MIN
. If the temperature is below T
Function
TACH4
THERM
SMBALERT
GPIO
Bit Setting
<0> ALERT Enable = 1
ADT7467
MIN