AT90PWM3B-16SU Atmel, AT90PWM3B-16SU Datasheet - Page 216

• Manufacturer Part Number: AT90PWM3B-16SU
• Description: IC MCU AVR RISC 8K FLASH 32-SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3B-16SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-SOIC (7.5mm Width)
• Processor Series: AT90PWMx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 27
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• On-chip Dac: 1-chx10-bit
• Controller Family/series: AVR PWM
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 16MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Internal
Manchester
Clock
Resynchronize
Internal
Manchester
Clock
Manchester
Data
Manchester
Decoder
Counter
Edge Detection
Space
Internal
Manchester
Clock
Counter
Overflow
AT90PWM2/3/2B/3B
Start Bit
Start Bit
N1
Figure 19-5. Manchester Frame error detection
Note:
When a Manchester framing error is detected the FEM bit and RxC bit are set at the same time.
This allows the application to execute the reception complete interrupt subroute when this error
conditon is detected.
When a Manchester framing error is detected, the EUSART receiver immediately enters in a
new start bit detection phase. Thus when a Manchester framing error is detected within a frame,
the receiver will process the rest of the frame as a new incomming frame and generate other
FEM errors.
N1/2
Counter Overflow = MBURR[H:L]
Bit 1
N2
N2/4
N2/2
front shift
Transition outside
the detect window
Bit 2
N3
Start Bit
Start Bit
N1
Bit 1
N2
The counter reaches the counter overflow
value without reaching a manchester edge
Framing Error
Bit 2
back shift
N3
4317J–AVR–08/10