MC9S12E64CFUE Freescale Semiconductor, MC9S12E64CFUE Datasheet - Page 316

• Manufacturer Part Number: MC9S12E64CFUE
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 60
• Interface Type: SCI/SPI
• On-chip Adc: 16-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 12
• Processor Series: S12E
• Core: HCS12
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 58
• Ram Memory Size: 4KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 10 Inter-Integrated Circuit (IICV2)
10.4.1.8
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
10.4.1.9
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it.If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
10.4.2
This is the basic mode of operation.
10.4.3
IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate
normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module
enters a power conservation state during wait mode. In the later case, any transmission or reception in
progress stops at wait mode entry.
10.4.4
The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC
register states.
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SCL1
SCL2
SCL
Operation in Run Mode
Operation in Wait Mode
Operation in Stop Mode
Handshaking
Clock Stretching
Internal Counter Reset
Figure 10-10. IIC-Bus Clock Synchronization
MC9S12E128 Data Sheet, Rev. 1.07
WAIT
Start Counting High Period
Freescale Semiconductor