EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 279

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

DS785UM1
8.6.2 Example of Breshenham’s Algorithm Line Draw
The final step is to wait for an interrupt or poll for EN = ‘0’ in the BLOCKCTRL register. When
the EN bit becomes cleared to ‘0’, the line draw function is complete.
To achieve the following display and pattern, follow Steps 1 to 14 in this section.
The following sequence describes how to set up those registers that are used for a
Breshenham’s algorithm line draw.
9. Setup BLKDESTWIDTH Register
10.Setup BLKDESTHEIGHT Register
11.Setup BLOCKCTRL Register
1. Write XINIT = 0x800 (2048) and YINIT = 0x800 to the
2. Write PTTN = 0x00FF and CNT = 0xF to the
3. Write LEN = 0x140 to the
4. Write SPEL = 0x8 and EPEL = 0x0 to the
• Display size is 640 x 480 x 16-bits per pixel
• Display memory starts at physical location 0x0000_0000
• Pattern is 8 transparent pixels and 8 white pixels
• X2 = 20, X1 = 101
• Y2 = 20, Y1 = 301
(1 / # of 16-bit pixels in word) = 640 x 1/2 = 320 = 0x140
register.
register.
Write ‘abs(X2 -X1) modulo 4096, minus 1’ to the WIDTH field in the
Write ‘abs(Y2 - Y1) / 4096, minus 1’ to the HEIGHT field in the
A. Clear the
B. Set the LINE bit to ‘1’
C. If X2 > X1, set the DXDIR bit to ‘1’, else set the DXDIR bit to ‘0’
D. If Y2 > Y1, set the DYDIR bit to ‘1’, else set the DYDIR bit to ‘0’
E. Either set the BG bit to ‘1’ to use the background color specified in
F. Set the P bits to the value for the desired BPP color depth
G. If interrupts are desired, set the INTEN bit to ‘1’
H. Set the EN bit to ‘1’
register or set the BG bit to ‘0’ for transparent background.
“BLOCKCTRL”
Copyright 2007 Cirrus Logic
“DESTLINELENGTH”
register by writing 0x0000_0000 to it.
“DESTPIXELSTRT”
“LINEPATTRN”
register, where LEN = 640 (pixels) x 1/2
“LINEINIT”
register
register, where:
“BLKDESTHEIGHT”
register
“BLKDESTWIDTH”
Graphics Accelerator
EP93xx User’s Guide
“BACKGROUND”
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