EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 717
EP9315-CBZ
Manufacturer Part Number
EP9315-CBZ
Description
IC ARM9 SOC ENH UNIV 352PBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9315-CBZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
352-BGA
Controller Family/series
(ARM9)
No. Of I/o's
16
Cpu Speed
200MHz
No. Of Timers
5
Digital Ic Case Style
BGA
Supply Voltage Range
1.65V To 1.94V, 3V To 3.6V
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9315A-Z
Case
BGA
Dc
06+
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1144 - KIT DEVELOPMENT EP9315 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1139
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9315-CBZ
Manufacturer:
CIRRUS
Quantity:
20 000
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DS785UM1
23.5.6 Motorola
23.5.6.1 SPO Clock Polarity
23.5.6.2 SPH Clock Phase
23.5.7 Motorola SPI Format with SPO=0, SPH=0
SFRMOUT /
SCLKOUT /
The Motorola SPI interface is a four-wire interface where the SFRMOUT signal behaves as a
slave select. The main feature of the Motorola SPI format is that the inactive state and phase
of the SCLKOUT signal are programmable through the SPO and SPH bits within the control
register,
When the SPO clock polarity control bit is LOW, it produces a steady state low value on the
SCLKOUT pin. If the SPO clock polarity control bit is HIGH, a steady state high value is
placed on the SCLKOUT pin when data is not being transferred.
The SPH control bit selects the clock edge that captures data and allows it to change state. It
has the most impact on the first bit transmitted by either allowing or not allowing a clock
transition before the first data capture edge.
When the SPH phase control bit is LOW, data is captured on the first clock edge transition. If
the SPH clock phase control bit is HIGH, data is captured on the second clock edge
transition.
Single and continuous transmission signal sequences for Motorola SPI format with SPO=0,
SPH=0 are shown in
SFRMIN
SCLKIN
SSPTXD
SSPRXD
SSPOE
Figure 23-3. Motorola SPI Frame Format (Single Transfer) with SPO=0 and SPH=0
“SSPCR0” on page
®
SPI Frame Format
MS B
MS B
Figure 23-3
23-13.
Copyright 2007 Cirrus Logic
and
Figure 23-4 on page
4 t o 16 bi t s
23-6.
Synchronous Serial Port
EP93xx User’s Guide
LS B
LS B
Q
23-5
23
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