EP9315-CBZ Cirrus Logic Inc, EP9315-CBZ Datasheet - Page 373

• Manufacturer Part Number: EP9315-CBZ
• Description: IC ARM9 SOC ENH UNIV 352PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CBZ

• Core Size: 16/32-Bit
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Controller Family/series: (ARM9)
• No. Of I/o's: 16
• Cpu Speed: 200MHz
• No. Of Timers: 5
• Digital Ic Case Style: BGA
• Supply Voltage Range: 1.65V To 1.94V, 3V To 3.6V
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• Case: BGA
• Dc: 06+
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1139

Descriptor Processor Receive Registers
RXDQBAdd
DS785UM1
31
15
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
RxAct:
QID:
0x8001_0090 - Read/Write
0x0000_0000
Unchanged
Receive Descriptor Queue Base Address register. The Receive Descriptor
Queue Base Address defines the system memory address of the receive
descriptor queue, this address is used by the MAC to reload the Receive
Current Descriptor Address whenever the end of the descriptor queue is
reached. The base address should be set at initialization time and must be set
to a word aligned memory address.
RDBA:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Receive Active. When this bit is set, the channel is active
and may be in the process of transferring receive data.
Following a RxDisable Command (Bus Master Control),
when transfers have been halted, this bit is cleared.
Queue ID. The queue ID reflects the current or last DMA
queue active on the AHB bus. When an AHB error halts
DMA operation, this field may be used to determine the
queue that caused the error.
ID
000 - Receive data
001 - Transmit data
010 - Receive status
011 - Transmit status
100 - Receive descriptor
101 - Transmit descriptor
Receive Descriptor Base Address.
24
8
Type of transfer
RDBA
RDBA
23
7
22
6
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
19
3
EP93xx User’s Guide
18
2
17
1
16
9-71
0
9