HD64F7044F28V Renesas Electronics America, HD64F7044F28V Datasheet - Page 358

• Manufacturer Part Number: HD64F7044F28V
• Description: IC SUPERH MCU FLASH 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD64F7044F28V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Instruction Descriptions
6.3.11
Description: Adds 1 to the top word of the Sx and Sy operands, stores the result in the upper word
of the Dz operand, and clears the bottom word of the Dz operand with zeros. When conditions are
specified for DCT and DCF, the instruction is executed when those conditions are TRUE. When
they are FALSE, the instruction is not executed.
When conditions are not specified, the DC bit of the DSR register is updated according to the
specifications for the CS bits. The N, Z, V, and GT bits of the DSR register are also updated. If
conditions are specified, the DC, N, Z, V, and GT bits are not updated even is the conditions were
true and the instruction was executed.
Note:
Rev. 5.00 Jun 30, 2004 page 342 of 512
REJ09B0171-0500O
Format
PINC Sx,Dz
PINC Sy,Dz
DCT PINC
Sx,Dz
DCT PINC
Sy,Dz
DCF PINC
Sx,Dz
DCF PINC
Sy,Dz
The bottom word of the destination register is ignored when the DC bit is updated.
[if cc] PINC (Increment by 1 with Condition): DSP Arithmetic Operation
Instruction
Abstract
MSW of Sx + 1
Dz, clear LSW of Dz
MSW of Sy + 1
Dz, clear LSW of Dz
If DC = 1, MSW of Sx + 1
MSW of Dz, clear LSW of
Dz; if 0, nop
If DC = 1, MSW of Sy + 1
MSW of Dz, clear LSW of
Dz; if 0, nop
If DC = 0, MSW of Sx + 1
MSW of Dz, clear LSW of
Dz; if 1, nop
If DC = 0, MSW of Sy + 1
MSW of Dz, clear LSW of
Dz; if 1, nop
MSW of
MSW of
111110**********
10011001xx00zzzz
111110**********
1011100100yyzzzz
111110**********
10011010xx00zzzz
111110**********
1011101000yyzzzz
111110**********
10011011xx00zzzz
111110**********
1011101100yyzzzz
Code
1
1
1
1
1
1
Cycle
DC Bit
Update
Update
—
—
—
—
SH-1
—
—
—
—
—
—
Instructions
Applicable
SH-2
—
—
—
—
—
—
SH-
DSP