HD64F7044F28V Renesas Electronics America, HD64F7044F28V Datasheet - Page 440

• Manufacturer Part Number: HD64F7044F28V
• Description: IC SUPERH MCU FLASH 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD64F7044F28V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Pipeline Operation
Contention
MA contends with IF
Causes multiplier contention (cont)
MA contends with IF
Causes DSP operation contention
MA contends with IF
Causes multiplier contention
Causes DSP operation contention
Causes memory load contention
Causes MOVX.W, MOVY.W,
MOVS.W or MOVS.L instruction
contention
Note:
7.3.2
Instruction execution speed can be increased by trying, at the programming stage, to keep
contention from occurring. Follow these rules when writing programs to minimize contention:
1. A 32-bit DSP instruction can require up to three memory accesses per cycle: one instruction
2. Follow instructions that compute a value in the DSP unit and write it to a DSP register with
3. Instruction fetch (IF) can conflict with an SH data memory access (MA) because both use the
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REJ09B0171-0500O
(I-bus), one X-data (X-bus), and one Y-data (Y-bus). The SH-DSP has four independently
accessible on-chip memory areas: X-ROM, X-RAM, Y-ROM, and Y-RAM. If more than one
access is performed in the same memory area in a cycle, a stall occurs. Locate the program
(instructions) and the data arrays that the program accesses in different on-chip memory areas.
This prevents memory bank contention in DSP instructions.
instructions that do not store the same register to memory. This prevents DSP register
contention because storing a DSP register that was the destination of a DSP calculation in the
previous cycle will cause a stall.
same bus. Whether the instruction fetch occurs in a specific cycle depends on the locations and
size (16 bit or 32 bit) of the preceding instructions. Try to locate the SH instructions that
perform memory access at longword boundries in on-chip memory and use a 16-bit instruction
as the next instruction. This prevents contention between memory accesses and instruction
fetches.
* Indicates the normal number of cycles. The figures in parentheses are the cycles when
Increasing Instruction Execution Speed
contention also occurs with the previous instruction.
Cycles
2 (to 3)*
2 (to 4)*
2 (to 4)*
1
1
1
Stages
7
9
9
4
5
5
Instructions
Multiply and accumulate calculation
instructions
Double-length multiplication instructions
Double-length multiply and accumulate
calculation instructions
MOVS.W (store) and MOVS.L (store)
instructions
STS instruction (except PR)
PLDS and PSTS instructions