PIC18F45J10-I/PT Microchip Technology, PIC18F45J10-I/PT Datasheet - Page 119

IC PIC MCU FLASH 16KX16 44TQFP

PIC18F45J10-I/PT

Manufacturer Part Number
PIC18F45J10-I/PT
Description
IC PIC MCU FLASH 16KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F45J10-I/PT

Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
32
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
40MHz
No. Of Timers
3
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1024 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164330 - MODULE SKT FOR 44TQFP 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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FIGURE 11-2:
11.2
Timer1 can be configured for 16-bit reads and writes
(see Figure 11-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 High Byte Buffer register. This
provides the user with the ability to accurately read all 16
bits of Timer1 without having to determine whether a
read of the high byte, followed by a read of the low byte,
has become invalid due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H Buffer register. The Timer1 high
byte is updated with the contents of TMR1H when a
write occurs to TMR1L. This allows a user to write all
16 bits to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer1 High Byte Buffer register.
Writes to TMR1H do not clear the Timer1 prescaler.
The prescaler is only cleared on writes to TMR1L.
© 2008 Microchip Technology Inc.
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T1CKI
Timer1 16-Bit Read/Write Mode
T1OSI
Timer1 Oscillator
T1OSCEN
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
(1)
TMR1CS
(CCP Special Event Trigger)
Clear TMR1
Internal
Clock
F
OSC
/4
1
0
Timer1 Clock Input
PIC18F45J10 FAMILY
Prescaler
1, 2, 4, 8
11.3
An on-chip crystal oscillator circuit is incorporated
between pins T1OSI (input) and T1OSO (amplifier
output). It is enabled by setting the Timer1 Oscillator
Enable bit, T1OSCEN (T1CON<3>). The oscillator is a
low-power circuit rated for 32 kHz crystals. It will continue
to run during all power-managed modes. The circuit for a
typical oscillator is shown in Figure 11-3. Table 11-1
shows the capacitor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator.
FIGURE 11-3:
Note:
2
Timer1 Oscillator
27 pF
27 pF
TMR1L
C1
C2
See the Notes with Table 11-1 for additional
information about capacitor selection.
8
Synchronize
8
Sleep Input
32.768 kHz
XTAL
Detect
High Byte
TMR1H
TMR1
EXTERNAL
COMPONENTS FOR THE
TIMER1 OSCILLATOR
8
8
8
T1OSI
T1OSO
Internal Data Bus
PIC18F45J10
1
0
Read TMR1L
Write TMR1L
DS39682D-page 117
Set
TMR1IF
on Overflow
Timer1
On/Off

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