PIC18F45J10-I/PT Microchip Technology, PIC18F45J10-I/PT Datasheet - Page 157

• Manufacturer Part Number: PIC18F45J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.4
The MSSP module in I
master and slave functions (including general call
support) and provides interrupts on Start and Stop bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
• Serial clock (SCLx) – RC3/SCK1/SCL1 or
• Serial data (SDAx) – RC4/SDI1/SDA1 or
The user must configure these pins as inputs by setting
the associated TRIS bits.
FIGURE 15-7:
© 2008 Microchip Technology Inc.
Note:
SDAx
SCLx
RD6/SCK2/SCL2
RD5/SDI2/SDA2
Only port I/O names are used in this diagram for
the sake of brevity. Refer to the text for a full list of
multiplexed functions.
I
2
C Mode
Read
Shift
Clock
MSb
SSPxADD reg
Address Mask
Stop bit Detect
Match Detect
SSPxBUF reg
SSPxSR reg
MSSP BLOCK DIAGRAM
(I
Start and
2
2
C mode fully implements all
C™ MODE)
LSb
Write
Addr Match
Set, Reset
S, P bits
(SSPxSTAT reg)
Internal
Data Bus
PIC18F45J10 FAMILY
15.4.1
The MSSP module has six registers for I
These are:
• MSSP Control Register 1 (SSPxCON1)
• MSSP Control Register 2 (SSPxCON2)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
• MSSP Shift Register (SSPxSR) – Not directly
• MSSP Address Register (SSPxADD)
SSPxCON1, SSPxCON2 and SSPxSTAT are the
control and status registers in I
SSPxCON1 and SSPxCON2 registers are readable
and writable. The lower 6 bits of the SSPxSTAT are
read-only. The upper two bits of the SSPxSTAT are
read/write.
Many of the bits in SSPxCON2 assume different
functions, depending on whether the module is operat-
ing in Master or Slave mode; bits<5:2> also assume
different names in Slave mode. The different aspects of
SSPxCON2 are shown in Register 15-5 (for Master
mode) and Register 15-6 (Slave mode).
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data bytes
are written to or read from.
SSPxADD register holds the slave device address
when the MSSP is configured in I
the MSSP is configured in Master mode, the lower
seven bits of SSPxADD act as the Baud Rate
Generator reload value.
In receive operations, SSPxSR and SSPxBUF together
create a double-buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
During
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
(SSPxBUF)
accessible
Note:
transmission,
REGISTERS
Disabling the MSSP module by clearing
the SSPEN (SSPxCON1<5>) bit may not
reset the module. It is recommended to
clear the SSPxSTAT, SSPxCON1 and
SSPxCON2 registers and select the mode
prior to setting the SSPEN bit to enable
the MSSP module.
the
2
C mode operation. The
2
SSPxBUF
C Slave mode. When
DS39682D-page 155
2
C operation.
is
not