PIC18F45J10-I/PT Microchip Technology, PIC18F45J10-I/PT Datasheet - Page 240

• Manufacturer Part Number: PIC18F45J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F45J10 FAMILY
20.2
For PIC18F45J10 family devices, the WDT is driven by
the INTRC oscillator. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is selected
by a multiplexor, controlled by the WDTPS bits in Config-
uration Register 2H. Available periods range from about
4 ms to 135 seconds (2.25 minutes) depending on volt-
age, temperature and Watchdog postscaler. The WDT
and postscaler are cleared whenever a SLEEP or
CLRWDT instruction is executed, or a clock failure
(primary or Timer1 oscillator) has occurred.
FIGURE 20-1:
REGISTER 20-9:
TABLE 20-2:
DS39682D-page 238
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
Note 1:
RCON
WDTCON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
WDTPS3:WDTPD0
Name
All Device Resets
u-0
INTRC Oscillator
—
Watchdog Timer (WDT)
This bit has no effect if the Configuration bit, WDTEN, is enabled.
SWDTEN
CLRWDT
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is off
Sleep
IPEN
Bit 7
SUMMARY OF WATCHDOG TIMER REGISTERS
—
U-0
—
WDT BLOCK DIAGRAM
WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit 6
Enable WDT
—
—
W = Writable bit
‘1’ = Bit is set
U-0
—
WDT Counter
Bit 5
CM
—
÷128
INTRC Control
4
U-0
Bit 4
—
Programmable Postscaler
RI
—
1:1 to 1:32,768
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Bit 3
TO
—
20.2.1
The WDTCON register (Register 20-2) is a readable
and writable register. The SWDTEN bit enables or
disables WDT operation.
U-0
—
Note 1: The CLRWDT and SLEEP instructions
2: When a CLRWDT instruction is executed,
Bit 2
PD
WDT
—
(1)
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
the postscaler count will be cleared.
Reset
U-0
—
Bit 1
POR
—
© 2008 Microchip Technology Inc.
x = Bit is unknown
SWDTEN
U-0
Bit 0
BOR
—
Wake-up from
Power-Managed
Modes
WDT
Reset
Reset Values
SWDTEN
on page
R/W-0
44
44
bit 0
(1)