PIC18F1320-E/P Microchip Technology, PIC18F1320-E/P Datasheet - Page 20
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PIC18F1320-E/P
Manufacturer Part Number
PIC18F1320-E/P
Description
IC MCU FLASH 4KX16 EEPROM 18DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1220-ISO.pdf
(308 pages)
3.PIC18F1220-ISO.pdf
(8 pages)
4.PIC18F1220-ISO.pdf
(6 pages)
5.PIC18F1220-ISO.pdf
(10 pages)
6.PIC18F1220-ISO.pdf
(4 pages)
7.PIC18F1320-ISS.pdf
(36 pages)
8.PIC18F1220-EP.pdf
(310 pages)
Specifications of PIC18F1320-E/P
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
7-ch x 10-bit
Package
18PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP180 - DEVICE ADAPTER 18F1320 PDIP 18LDACICE0202 - ADAPTER MPLABICE 18P 300 MIL
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC18FX220/X320
4.0
4.1
Data EEPROM is accessed one byte at a time via an
Address Pointer, EEADR, and a Data Latch, EEDATA.
Data EEPROM is read by loading EEADR with the
desired memory location and initiating a memory read
by appropriately configuring the EECON1 register. The
data will be loaded into EEDATA, where it may be
serially output on PGD via the 4-bit command, ‘0010’
(Shift Out Data Holding register). A delay of P6 must be
introduced after the falling edge of the 8th PGC of the
operand to allow PGD to transition from an input to an
output. During this time, PGC must be held low (see
Figure 4-2).
The command sequence to read a single byte of data
is shown in Table 4-1.
TABLE 4-1:
FIGURE 4-2:
DS39592F-page 20
Step 1: Direct access to data EEPROM.
Step 2: Set the data EEPROM Address Pointer.
Step 3: Initiate a memory read.
Step 4: Load data into the Serial Data Holding register.
Note 1:
Command
PGC
PGD
0000
0000
0000
0000
0000
0000
0000
0010
4-Bit
READING THE DEVICE
Read Data EEPROM Memory
The <LSB> is undefined. The <MSB> is the data.
1
0
2
1
9E A6
9C A6
0E <Addr>
6E A9
80 A6
50 A8
6E F5
<LSB><MSB>
READ DATA EEPROM MEMORY
3
0
SHIFT OUT DATA HOLDING REGISTER TIMING (
Data Payload
4
0
P5
PGD = Input
1
2
3
4
BCF
BCF
MOVLW <Addr>
MOVWF EEADR
BSF
MOVF
MOVWF TABLAT
Shift Out Data
5
6
EECON1, EEPGD
EECON1, CFGS
EECON1, RD
EEDATA, W, 0
7
8
P6
(1)
9
LSb
FIGURE 4-1:
P14
10 11
1
2
PGD = Output
Core Instruction
12
Shift Data Out
3
13
4
No
0010
14
5
15 16
Move to TABLAT
6
Shift Out Data
)
READ DATA EEPROM
FLOW
2010 Microchip Technology Inc.
Address
Done?
Read
Done
Start
MSb
Byte
Set
P5A
Yes
Fetch Next 4-Bit Command
1
n
PGD = Input
2
n
3
n
4
n