PIC18F27J53-I/ML Microchip Technology, PIC18F27J53-I/ML Datasheet - Page 230
![IC PIC MCU 128KB FLASH 28QFN](/photos/18/33/183309/qfn-28_sml.jpg)
PIC18F27J53-I/ML
Manufacturer Part Number
PIC18F27J53-I/ML
Description
IC PIC MCU 128KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18LF24J10-ISS.pdf
(32 pages)
2.PIC18F26J13-ISS.pdf
(496 pages)
3.PIC18F26J53-ISS.pdf
(586 pages)
4.PIC18F26J53-ISS.pdf
(12 pages)
Specifications of PIC18F27J53-I/ML
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
*
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2.15 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.8 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
2.15 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Controller Family/series
PIC18
Cpu Speed
48MHz
Embedded Interface Type
I2C, SPI, USART
Digital Ic Case Style
QFN
Supply Voltage Range
1.8V To 5.5V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18LF24J10-ISS PDF datasheet
- PIC18F26J13-ISS PDF datasheet #2
- PIC18F26J53-ISS PDF datasheet #3
- PIC18F26J53-ISS PDF datasheet #4
- Current page: 230 of 496
- Download datasheet (5Mb)
PIC18(L)F2X/4XK22
15.5.3.3
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt
generation after the 8th falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
Figure 15-18
Address Slave Transmission with AHEN enabled.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave hardware automatically clears the CKP bit
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
15. Slave hardware copies the ACK value into the
16. Steps 10-15 are repeated for each byte
17. If the master sends a not ACK the slave
DS41412D-page 230
Note: SSPxBUF cannot be loaded until after the
Note: Master must send a not ACK on the last byte
Bus starts Idle.
Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
Master sends matching address with R/W bit
set. After the 8th falling edge of the SCLx line
the CKP bit is cleared and SSPxIF interrupt is
generated.
Slave software clears SSPxIF.
Slave software reads ACKTIM bit of SSPxCON3
register, and R/W and D/A of the SSPxSTAT
register to determine the source of the interrupt.
Slave reads the address value from the SSPxBUF
register clearing the BF bit.
Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSPxCON2 register accordingly.
Slave sets the CKP bit releasing SCLx.
Master clocks in the ACK value from the slave.
and sets SSPxIF after the ACK if the R/W bit is
set.
SSPxBUF setting the BF bit.
sends an ACK value on the 9th SCLx pulse.
ACKSTAT bit of the SSPxCON2 register.
transmitted to the master from the slave.
releases the bus allowing the master to send a
Stop and end the communication.
ACK.
to ensure that the slave releases the SCLx
line to receive a Stop.
7-bit Transmission with Address
Hold Enabled
displays a standard waveform of a 7-bit
Preliminary
2010 Microchip Technology Inc.
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