PIC18F67K90-I/MRRSL Microchip Technology, PIC18F67K90-I/MRRSL Datasheet - Page 115
![MCU PIC 128K FLASH XLP 64QFN](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67K90-I/MRRSL
Manufacturer Part Number
PIC18F67K90-I/MRRSL
Description
MCU PIC 128K FLASH XLP 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F67K90-I/MRRSL
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
3828Byte
Cpu Speed
16MIPS
No. Of Timers
11
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
53
Number Of Timers
11
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DM163030, DM180021, DM183026-2, DM183032, DV164131, MA180027
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7.5
The programming block is 32 words or 64 bytes for
PIC18FX5K90
64 words or 128 bytes for PIC18FX7K90 devices.
Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 64 holding registers for PIC18FX5K90 and
PIC18FX6K90 devices and 128 holding registers for
PIC18FX7K90 used by the table writes for programming.
Since the Table Latch (TABLAT) is only a single byte, the
TBLWT instruction may need to be executed 64 times for
each programming operation. All of the table write oper-
ations will essentially be short writes because only the
holding registers are written. At the end of updating the
64 or 128 holding registers, the EECON1 register must
be written to in order to start the programming operation
with a long write.
FIGURE 7-5:
7.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
8.
9.
2010 Microchip Technology Inc.
TBLPTR = xxxxx0
Read the 64 or 128 bytes into RAM.
Update the data values in RAM as necessary.
Load the Table Pointer register with the address
being erased.
Execute the row erase procedure.
Load the Table Pointer register with the address
of the first byte being written.
Write the 64 or 128 bytes into the holding
registers with auto-increment.
Set the EECON1 register for the write operation:
• Set the EEPGD bit to point to program memory
• Clear the CFGS bit to access program memory
• Set WREN to enable byte writes
Disable the interrupts.
Write 0x55 to EECON2.
Writing to Flash Program Memory
FLASH PROGRAM MEMORY WRITE
SEQUENCE
Holding Register
and
8
TABLE WRITES TO FLASH PROGRAM MEMORY
PIC18FX6K90
TBLPTR = xxxxx1
devices,
Holding Register
8
and
Preliminary
Program Memory
TBLPTR = xxxxx2
Write Register
TABLAT
PIC18F87K90 FAMILY
The long write is necessary for programming the inter-
nal Flash. Instruction execution is halted while in a long
write cycle. The long write is terminated by the internal
programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device.
10. Write 0xAA to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. Re-enable the interrupts.
13. Verify the memory (table read).
An example of the required code is shown in
Example 7-3 on the following page.
Note:
Holding Register
Note:
Note:
The CPU will stall for duration of the write for T
(see parameter D133A).
8
registers before executing a write operation.
The default value of the holding registers on
device Resets and after write operations is
FFh. A write of FFh to a holding register
does not modify that byte. This means that
individual bytes of program memory may be
modified, provided that the change does not
attempt to change any bit from a ‘0’ to a ‘1’.
When modifying individual bytes, it is not
necessary to load all 64 or 128 holding
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the 64 or
128 bytes in the holding register.
Self-write
EEPROM memory cannot be done while
running in LP Oscillator mode (Low-Power
mode). Therefore, executing a self-write
will put the device into High-Power mode.
TBLPTR = xxxx3F
execution
DS39957B-page 115
Holding Register
to
Flash
8
and
IW
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