PIC18F67K90-I/MRRSL Microchip Technology, PIC18F67K90-I/MRRSL Datasheet - Page 532
![MCU PIC 128K FLASH XLP 64QFN](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67K90-I/MRRSL
Manufacturer Part Number
PIC18F67K90-I/MRRSL
Description
MCU PIC 128K FLASH XLP 64QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18F67K90-I/MRRSL
Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC18
Eeprom Memory Size
1024Byte
Ram Memory Size
3828Byte
Cpu Speed
16MIPS
No. Of Timers
11
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
53
Number Of Timers
11
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DM163030, DM180021, DM183026-2, DM183032, DV164131, MA180027
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F87K90 FAMILY
FIGURE 31-14:
TABLE 31-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
DS39957B-page 532
Param
70
70A
71
71A
72
72A
73A
74
75
76
77
78
79
80
82
83
Note 1:
No.
SSx
SCKx
(CKP = 0 )
SCKx
(CKP = 1 )
SDOx
SDIx
Note:
2:
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
SS
SS
SS
SC
SC
SC
SC
SS
SC
SC
SC
SC
SS
SC
SC
Symbol
B
DO
DO
2
Requires the use of Parameter #73A.
Only if Parameter #71A and #72A are used.
L2
L2
L2
L2WB SSx to write to SSPxBUF
H2
H2
L2
H2
L2
H
L
H2
L2
R
F
B
R
F
DO
SC
SC
DO
SS
DI
DO
SS
Refer to Figure 31-3 for load conditions.
DO
DI
L
H
L,
V SDOx Data Output Valid after SSx Edge
H,
L
V
H,
V,
Z SSx to SDOx Output High-Impedance
SCKx Input High Time
SCKx Output Rise Time (Master mode)
SSx to SCKx or SCKx Input
(Slave mode)
SCKx Input Low Time
(Slave mode)
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 T
Hold Time of SDIx Data Input to SCKx Edge
SDOx Data Output Rise Time
SDOx Data Output Fall Time
SCKx Output Fall Time (Master mode)
SDOx Data Output Valid after SCKx Edge
SSx after SCKx Edge
82
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
70
MSb In
MSb
74
71
75, 76
Characteristic
72
bit 6 - - - - - - 1
bit 6 - - - - 1
Preliminary
Continuous
Single Byte
Continuous
Single Byte
80
LSb In
LSb
1.25 T
1.25 T
1.5 T
3 T
3 T
Min
CY
40
40
CY
40
10
—
—
—
—
—
—
CY
CY
CY
CY
83
+ 40
+ 40
+ 30
+ 30
2010 Microchip Technology Inc.
77
Max Units Conditions
25
50
50
—
—
—
—
—
—
—
25
25
25
50
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)
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