ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet
ST10F269Z2Q6
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ST10F269Z2Q6 Summary of contents
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MCU WITH MAC UNIT, 256 KBYTE FLASH MEMORY AND 12 KBYTE RAM ■ HIGH PERFORMANCE 32MHz CPU WITH DSP FUNCTION – 16-BIT CPU WITH 4-STAGE PIPELINE – 62.5ns INSTRUCTION CYCLE TIME AT 32MHz MAX CPU CLOCK – MULTIPLY/ACCUMULATE UNIT ...
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ST10F269-T3 TABLE OF CONTENTS 1 - INTRODUCTION ........................................................................................................ 2 - PIN DATA ................................................................................................................... 3 - FUNCTIONAL DESCRIPTION ................................................................................... 4 - MEMORY ORGANIZATION ....................................................................................... 5 - INTERNAL FLASH MEMORY ................................................................................... 5.1 - OVERVIEW ................................................................................................................ 5.2 - OPERATIONAL OVERVIEW ...................................................................................... 5.3 - ...
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TABLE OF CONTENTS 8 - INTERRUPT SYSTEM ............................................................................................... 8.1 - EXTERNAL INTERRUPTS ......................................................................................... 8.2 - INTERRUPT REGISTERS AND VECTORS LOCATION LIST .................................. 8.3 - INTERRUPT CONTROL REGISTERS ....................................................................... 8.4 - EXCEPTION AND ERROR TRAPS LIST ................................................................... 9 - CAPTURE/COMPARE (CAPCOM) ...
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ST10F269-T3 TABLE OF CONTENTS 13 - A/D CONVERTER ...................................................................................................... 14 - SERIAL CHANNELS ................................................................................................. 14.1 - ASYNCHRONOUS / SYNCHRONOUS SERIAL INTERFACE (ASCO) ..................... 14.1.1 - ASCO in Asynchronous Mode .................................................................................... 14.1.2 - ASCO in Synchronous Mode ...................................................................................... 14.2 - HIGH ...
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TABLE OF CONTENTS 19.2.1 - Protected Power Down Mode ..................................................................................... 19.2.2 - Interruptible Power Down Mode ................................................................................. 20 - SPECIAL FUNCTION REGISTER OVERVIEW ......................................................... 20.1 - IDENTIFICATION REGISTERS ................................................................................. 20.2 - SYSTEM CONFIGURATION REGISTERS ................................................................ 21 - ELECTRICAL CHARACTERISTICS ......................................................................... ...
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... The Multiply/Accumulate unit is available as standard. This MAC unit adds powerful DSP functions to the ST10 architecture, but maintains full compatibility for existing code. – Flash control interface is now based on STMicroelectronics third stand-alone Flash memories, with an embedded Erase/Program Controller. This completely Figure 1 : Logic Symbol ...
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PIN DATA Figure 2 : Pin Configuration (top view) 1 P6.0/CS0 2 P6.1/CS1 P6.2/CS2 3 4 P6.3/CS3 5 P6.4/CS4 6 P6.5/HOLD 7 P6.6/HLDA 8 P6.7/BREQ 9 P8.0/CC16IO 10 P8.1/CC17IO 11 P8.2/CC18IO 12 P8.3/CC19IO 13 P8.4/CC20IO 14 P8.5/CC21IO 15 ...
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ST10F269-T3 Table 1 : Pin Description Symbol Pin Type P6 ... ... P8.0 - P8.7 9-16 I/O 9 I/O ... ... 16 I/O P7.0 ...
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Symbol Pin Type P2.0 - P2.7 47-54 I/O P2.8 - P2.15 57-64 47 I/O ... ... 54 I/O 57 I/O I ... ... 64 I P3.0 - P3.5 65-70, I/O P3.6 - P3.13, 73-80, I/O P3.15 81 I/O ...
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ST10F269-T3 Symbol Pin Type P4.0 –P4.7 85-92 I WR/WRL 96 O READY READY ALE 98 ...
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Symbol Pin Type P0L.0 - P0L.7, 100-107, I/O P0H.0 108, P0H.1 - P0H.7 111-117 P1L.0 - P1L.7 118-125 I/O P1H.0 - P1H.7 128-135 132 I 133 I 134 I 135 I XTAL1 138 I XTAL2 137 O RSTIN 140 I ...
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ST10F269-T3 Symbol Pin Type V 46, 72 82,93, 109, 126, 136, 144 V 18,45 55,71, 83,94, 110, 127, 139, 143 DC1 56 - DC2 17 - 12/162 Digital Supply Voltage during normal operation ...
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FUNCTIONAL DESCRIPTION The architecture of the ST10F269-T3 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The Figure 3 : Block Diagram 256K Byte Flash Memory 10K Byte XRAM P4.5 CAN1_RXD CAN1 P4.6 CAN1_TXD ...
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ST10F269- MEMORY ORGANIZATION The memory space of the ST10F269-T3 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16M Bytes. The entire memory ...
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Figure 4 : ST10F269-T3 On-chip Memory Mapping 14 05’0000 04’0000 10 0C 03’0000 02’0000 01’8000 05 04 01’0000 03 00’C000 02 00’6000 01 00’4000 00 00’0000 Data Absolute Page Memory Number Address * Bank 0L may be ...
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ST10F269-T3 XPERCON (F024h / 12h CAN1EN CAN1 Enable Bit ‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins can be used ...
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INTERNAL FLASH MEMORY 5.1 - Overview – 256K Byte on-chip Flash memory – Two possibilities of Flash mapping into the CPU address space – Flash memory can be used for code and data storage – 32-bit, zero waitstate ...
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ST10F269-T3 Instructions and Commands All operations besides normal read operations are initiated and controlled by command sequences written to the Flash Command Interface (CI). The Command Interface (CI) interprets words written to the Flash memory and enables one of the ...
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With the two possibilities for write protection - whole memory or block specific - a flexible installation of write protection is supported to protect the Flash memory or parts of it from unauthorized ...
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ST10F269-T3 Flash Status (see note for address FSB.7 Flash Status bit 7: Data Polling Bit Programming Operation: this bit outputs the complement of the bit 7 of the word being ...
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Flash Protection Register The Flash Protection register is a non-volatile register that contains the protection status. This register can be read by using the Read Protection Status (RP) command, and programmed by using the dedi- cated Set Protection ...
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ST10F269-T3 If the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to Read Mode not necessary to program the block with 0000h as ...
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Block Temporary Unprotection (BTU). This Instruction can be used to temporary unprotect all the blocks from Program / Erase protection. The Unprotection is disabled after a Reset cycle. The Block Temporary Unprotection command xxC1h must be given to enable Block ...
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ST10F269-T3 Table 3 : Instructions Instruction Mne Cycle Read/Reset RD 1+ Read/Reset RD 3+ Program Word PW 4 Block Erase BE 6 Chip Erase CE 6 Erase Suspend ES 1 Erase Resume ER 1 Set Block/Code Protection SP 4 Read ...
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Generally, command sequences cannot be written to Flash by instructions fetched from the Flash itself. Thus, the Flash commands must be written by instructions, executed from internal RAM or external memory. – Command cycles on the CPU interface need ...
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ST10F269-T3 5.5.2 - Basic Flash Access Control When accessing the Flash all command write addresses have to be located within the active Flash memory space. The active Flash memory space is that logical address range which is covered by the ...
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Programming Examples Most of the microcontroller programs are written in the C language where the data page pointers are automatically set by the compiler. But because the C compiler may use the not allowed direct addressing mode for ...
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ST10F269-T3 EXTS R11, #1 MOV [R12], R13 Data_Polling: EXTS R11, #1 MOV R7, [R12] MOV R6, R7 XOR R7, R13 JNB R7.7, Prog_OK JNB R6.5, Data_Polling EXTS R11, #1 MOV R7, [R12] XOR R7, R13 JNB R7.7, Prog_OK Prog_Error: MOV ...
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Example 3 Performing the Block Erase command We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been mapped to segment 1.The registers R11/R12 contain an address related to the block to be ...
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ST10F269-T3 5.6 - Bootstrap Loader The built-in bootstrap loader (BSL) of the ST10F269-T3 provides a mechanism to load the startup program through the serial interface after reset. In this case, no external memory or internal Flash memory is required for ...
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When the ST10F269-T3 has entered BSL mode, the following configuration is automatically set (values that deviate from the normal reset values, are marked): Watchdog Timer: Disabled Context Pointer CP: FA00h Stack Pointer SP: FA40h Register S0CON: 8011h Register S0BG: Acc. ...
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ST10F269-T3 Figure 7 : Memory Configuration after Reset Segment 255 Test Flash BSL mode active EA pin Code fetch from internal Flash area Data fetch from internal Flash area 5.6.3 - Loading the Startup Code After sending ...
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Choosing the Baud Rate for the BSL The calculation of the serial Baud rate for ASC0 from the length of the first zero Byte that is received, allows the operation of the bootstrap loader of the ST10F269-T3 with ...
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ST10F269- CENTRAL PROCESSING UNIT (CPU) The CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedi- cated SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator ...
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The System Configuration Register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT0 pins during reset. SYSCON (FF12h / 89h ...
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ST10F269-T3 6.1.1 - Features 6.1.1.1 - Enhanced Addressing Capabilities – New addressing modes including a double indi- rect addressing mode with pointer post-modifi- cation. – Parallel Data Move: this mechanism allows one operand move during Multiply-Accumulate in- structions without penalty. ...
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Instruction Set Summary The Table 4 lists the instructions of the ST10F269-T3. The various addressing modes, instruction opera- tion, parameters for conditional execution of instructions, opcodes and a detailed description of each instruction can be found in the ...
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ST10F269-T3 Table 4 : Instruction Set Summary Mnemonic JNBS Jump relative and set bit if direct bit is not set CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met CALLS Call absolute subroutine in any code segment PCALL Push ...
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Mnemonic CoMUL CoMULu CoMULus CoMULsu CoMUL- CoMULu- CoMULus- CoMULsu- CoMUL, rnd CoMULu, rnd CoMULus, rnd CoMULsu, rnd CoMAC CoMACu CoMACus CoMACsu CoMAC- CoMACu- CoMACus- CoMACsu- CoMAC, rnd CoMACu, rnd CoMACus, rnd CoMACsu, rnd CoMACR CoMACRu CoMACRus CoMACRsu CoMACR, rnd CoMACRu, ...
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ST10F269-T3 Mnemonic CoMACM CoMACMu CoMACMus CoMACMsu CoMACM- CoMACMu- CoMACMus- CoMACMsu- CoMACM, rnd CoMACMu, rnd CoMACMus, rnd CoMACMsu, rnd CoMACMR CoMACMRu CoMACMRus CoMACMRsu CoMACMR, rnd CoMACMRu, rnd CoMACMRus, rnd CoMACMRsu, rnd CoADD CoADD2 CoSUB CoSUB2 CoSUBR CoSUB2R CoMAX CoMIN CoLOAD CoLOAD- ...
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The Table 5 shows the various combinations of pointer post-modification for each of these 2 new address- ing modes. In this document the symbols “[Rw Table 5 : Pointer Post-modification Combinations for IDXi and Rwn Symbol ⊗]” stands for “[IDX ...
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ST10F269- EXTERNAL BUS CONTROLLER All of the external memory accesses are performed by the on-chip external bus controller. The EBC can be programmed to single chip mode when no external memory is required one of four ...
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Figure 11 : Chip Select Delay Normal Demultiplexed Segment (P4) Address (P1) ALE Normal CSx Unlatched CSx BUS (P0) RD BUS (P0) WR ALE Lengthen Demultiplexed Bus Cycle Data Data Read/Write Delay ST10F269-T3 Bus Cycle Data Data Read/Write Delay 43/162 ...
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ST10F269- INTERRUPT SYSTEM The interrupt response time for internal program execution is from 156.25ns to 375ns at 32MHz CPU clock. The ST10F269-T6 architecture supports several mechanisms for fast and flexible response to service requests that can be generated ...
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Interrupt Registers and Vectors Location List Table 7 shows all the available ST10F269-T3 interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers: Table 7 : Interrupt Sources Source of Interrupt or PEC ...
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ST10F269-T3 Table 7 : Interrupt Sources (continued) Source of Interrupt or PEC Service Request CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL ...
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Bit GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority ILVL Interrupt Priority ...
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ST10F269- CAPTURE/COMPARE (CAPCOM) UNITS The ST10F269-T3 has two 16 channels CAPCOM units as described in Figure 12. These support generation and control of timing sequences channels with a maximum resolution of 250ns at 32MHz ...
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Figure 13 : Block Diagram of CAPCOM Timers T0 and T7 Txl Input Control CPU X Clock GPT2 Timer T6 MUX Over / Underflow Edge Select Txl TxM TxIN Pin Txl Figure 14 : Block Diagram of CAPCOM Timers T1 ...
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ST10F269-T3 Table 9 : Compare Modes Compare Modes Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only ...
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GENERAL PURPOSE TIMER UNIT The GPT unit is a flexible multifunctional timer/ counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. ...
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ST10F269-T3 Figure 15 : Block Diagram of GPT1 T2EUD CPU Clock n 2 n=3...10 T2IN CPU Clock n 2 n=3...10 T3IN T3EUD T4IN CPU Clock n 2 n=3...10 T4EUD 10.2 - GPT2 The GPT2 module provides precise event control and ...
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Figure 16 : Block Diagram of GPT2 T5EUD CPU Clock n 2 n=2...9 T5IN CAPIN T6IN CPU Clock n 2 n=2...9 T6EUD U/D T5 GPT2 Timer T5 Mode Control Clear Capture GPT2 CAPREL T6 GPT2 Timer T6 Mode Control U/D ...
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ST10F269- PWM MODULE The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and Figure 17 : Block Diagram of ...
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PARALLEL PORTS 12.1 - Introduction The ST10F269-T3 MCU provides up to 111 I/O lines with programmable capabilities bring very flexible adaptation of this MCU to wide range of applications. ST10F269-T3 has 9 groups of I/O lines gathered as ...
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ST10F269-T3 Figure 18 : SFRs and Pins Associated with the Parallel Ports 56/162 ...
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I/O’s Special Features 12.2.1 - Open Drain Mode Some of the I/O ports of ST10F269-T3 support the open drain capability. This programmable feature may be used with an external pull-up resistor, in order to get an AND wired ...
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ST10F269-T3 Figure 20 : Hysteresis for Special Input Thresholds Hysteresis Input level Bit state 12.2.3 - Output Driver Control The port output control registers POCONx allow to select the port output driver characteristics of a port. The aim of these ...
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The table lists the defined POCON registers and the allocation of control bit-fields and port pins. Table 14 : Port Control Register Allocation Control Physical Register Address Address POCON0L F080h POCON0H F082h POCON1L F084h POCON1H F086h POCON2 F088h POCON3 F08Ah ...
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ST10F269-T3 12.2.4 - Alternate Port Functions Each port line has one associated programmable alternate input or output function. – PORT0 and PORT1 may be used as address and data lines when accessing external memory. – Port 2, Port 7 and ...
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PORT0 The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0, respectively. Both halves of PORT0 can be written (via a PEC transfer) without effecting the other half. P0L (FF00h / 80h) 15 ...
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ST10F269-T3 12.3.1 - Alternate Functions of PORT0 When an external bus is enabled, PORT0 is used as data bus or address/data bus. Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for I/O (provided that ...
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When an external bus mode is enabled, the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware. The input of the port output Buffer is disconnected from ...
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ST10F269-T3 12.4 - PORT1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halves of PORT1 can be written (via a PEC transfer) without effecting the other half. If this port is ...
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Figure 23 : PORT1 I/O and Alternate Functions Alternate Function P1H.7 P1H.6 P1H.5 P1H.4 P1H P1H.3 P1H.2 P1H.1 P1H.0 PORT1 P1L.7 P1L.6 P1L.5 P1L.4 P1L P1L.3 P1L.2 P1L.1 P1L.0 General Purpose Input/Output When an external bus mode is enabled, the ...
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ST10F269-T3 12.5 - Port 2 If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP2. Each port line can be switched into push/pull or open drain ...
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The direction of the pin should be set to output by the user, otherwise the pin will be in the high-impedance state and will not reflect the state of the output latch. As can be seen from the port structure ...
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ST10F269-T3 The pins of Port 2 combine internal bus data with alternate data output before the port latch input. Figure 26 : Block Diagram of a Port 2 Pin Write ODP2.y Open Drain Latch Read ODP2.y Write DP2.y Direction Latch ...
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Port 3 If this 15-bit port is used for general purpose I/O, the direction of each line can be configured by the corresponding direction register DP3. Most port lines can be switched into push-pull or open drain P3 ...
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ST10F269-T3 12.6.1 - Alternate Functions of Port 3 The pins of Port 3 serve for various functions which include external timer control lines, the two serial interfaces and the control lines BHE/WRH and CLKOUT. Table 16 : Port 3 Alternative ...
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Port 3 pins with alternate output functions are: T6OUT, T3OUT, TxD0, BHE and CLKOUT. When the on-chip peripheral associated with a Port 3 pin is configured to use both the alternate input and output function, the descriptions above apply to ...
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ST10F269-T3 Pin P3.12 (BHE/WRH) is another pin with an alternate output function, however, its structure is slightly different. After reset the BHE or WRH function must be used depending on the configuration. In either of these cases, there is no ...
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Port 4 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP4. P4 (FFC8h / E4h ...
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ST10F269-T3 12.7.1 - Alternate Functions of Port 4 During external bus cycles that use segmentation (address space above 64K Bytes) a number of Port 4 pins may output the segment address lines. The number of pins that is used for ...
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Figure 31 : Block Diagram of a Port 4 Pin Write DP4.y Direction Latch Read DP4.y Write P4.y Port Output Latch Read P4.y 1 “1” MUX 0 Alternate Function Enable Alternate Data 1 Output MUX 0 1 MUX 0 ST10F269-T3 ...
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ST10F269-T3 Figure 32 : Block Diagram of P4.4 and P4.5 Pins Write DP4.x Direction Latch Read DP4.x Write P4.x Port Output Latch Read P4.x CANy.RxD XPERCON.a (CANyEN) XPERCON.b (CANzEN) 76/162 1 “1” MUX 0 “0” 1 MUX Alternate Function 0 ...
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Figure 33 : Block Diagram of P4.6 and P4.7 Pins Write ODP4.x Open Drain Latch Read ODP4.x Write DP4.x Direction Latch Read DP4.x Write P4.x Port Output Latch Read P4.x CANy.TxD Data output XPERCON.a (CANyEN) XPERCON.b (CANzEN) 12.8 - Port ...
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ST10F269-T3 12.8.1 - Alternate Functions of Port 5 Each line of Port 5 is also connected to one of the multiplexer of the Analog/Digital Converter. All port lines (P5.15...P5.0) can accept analog signals (AN15...AN0 converted by the ADC. ...
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Port 5 pins have a special port structure (see Figure 35), first because input only port, and second because the analog input channels are directly connected to the pins rather than to the input latches. Figure 35 ...
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ST10F269-T3 DP6.y Port Direction Register DP6 Bit y DP6 Port line P6 input (high impedance) DP6 Port line P6 output ODP6 (F1CEH / E7H ...
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The chip select lines of Port 6 have an internal weak pull-up device. This device is switched on during reset. This feature is implemented to drive the chip select lines high during reset in order to avoid multiple chip selection. ...
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ST10F269-T3 Figure 38 : Block Diagram of Pin P6.5 (HOLD) Write ODP6.5 Open Drain Latch Read ODP6.5 Write DP6.5 Direction Latch Read DP6.5 Write P6.5 Port Output Latch Read P6.5 Alternate Data Input 82/162 Clock 1 MUX Input 0 Latch ...
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Port 7 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP7. Each port line can be switched into push-pull or open drain mode ...
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ST10F269-T3 12.10.1 - Alternate Functions of Port 7 The upper 4 lines of Port 7 (P7.7...P7.4) serve as capture inputs or compare (CC31IO...CC28IO) for the CAPCOM2 unit. The usage of the port lines by the CAPCOM unit, its accessibility via ...
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The structure of Port 7 differs in the way the output latches are connected to the internal bus and to the pin driver. Pins P7.3...P7.0 (POUT3...POUT0) Figure 40 : Block Diagram of Port 7 Pins P7.3...P7.0 Write ODP7.y Open Drain ...
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ST10F269-T3 Figure 41 : Block Diagram of Port 7 Pins P7.7...P7.4 Write ODP7.y Open Drain Latch Read ODP7.y Write DP7.y Direction Latch Read DP7.y 1 MUX Alternate 0 Data Output Write Port P7.y Compare Trigger Read P7.y 86/162 Output Latch ...
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Port 8 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the P8 (FFD4h / EAh P8.y Port ...
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ST10F269-T3 12.11.1 - Alternate Functions of Port 8 The 8 lines of Port 8 serve as capture inputs or as compare outputs (CC23IO...CC16IO) for the CAPCOM2 unit. The usage of the port lines by the CAPCOM unit, its accessibility via ...
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The structure of Port 8 differs in the way the output latches are connected to the internal bus and to the pin driver (see Figure 43). Pins P8.7...P8.0 Figure 43 : Block Diagram of Port 8 Pins P8.7...P8.0 Write ODP8.y ...
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ST10F269- A/D CONVERTER A 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit is integrated on-chip. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted ...
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SERIAL CHANNELS Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided by two serial interfaces: the asynchronous / synchronous serial channel (ASCO) and the high-speed synchronous serial channel (SSC). Two dedicated Baud rate generators ...
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ST10F269-T3 Asynchronous Mode Baud rates For asynchronous operation, the Baud rate generator provides a clock with 16 times the rate of the established Baud rate. Every received bit is sampled at the 7th, 8th and 9th cycle of this clock. ...
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ASCO in Synchronous Mode In synchronous mode, data are transmitted or received synchronously to a shift clock which is generated by the ST10F269-T3. Half-duplex communication up to 4MBaud (at 32MHz of f mode. Figure 45 : Synchronous Mode ...
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ST10F269-T3 Synchronous Mode Baud Rates For synchronous operation, the Baud rate generator provides a clock with 4 times the rate of the established Baud rate. The Baud rate for synchronous operation of serial channel ASC0 can be determined by the ...
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High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible communication between the ST10F269-T3 and other microcontrollers, microprocessors external peripherals. The SSC supports full-duplex and half-duplex synchronous communication. The serial clock signal can be ...
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ST10F269-T3 Baud Rate Generation The Baud rate generator is clocked by f stopped through the global enable bit SSCEN in register SSCCON. Register SSCBR is the dual-function Baud Rate Generator/Reload register. Reading SSCBR, while the SSC is enabled, returns the ...
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CAN MODULES The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active). Each on-chip CAN module can receive ...
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ST10F269-T3 The ST10F269-T3 also supports single CAN Bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Figure 48. Thanks to the OR-Wired Connection, only one transceiver is required. In this case the design ...
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REAL TIME CLOCK The Real Time Clock is an independent timer, which clock is directly derived from the clock oscillator on XTAL1 input so that it can keep on running even in Idle or Power down mode (if ...
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ST10F269-T3 16.1 - RTC registers 16.1.1 - RTCCON: RTC Control Register The functions of the RTC are controlled by the RTCCON control register. If the RTOFF bit is set, the RTC dividers and counters clock is disabled and registers can ...
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RTCPH & RTCPL: RTC PRESCALER Registers The 20-bit programmable prescaler divider is loaded with 2 registers. The 4 most significant bit are stored into RTCPH and the 16 Less significant bit are stored in RTCPL. In order to ...
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ST10F269-T3 When RTCD increments to reach 00000h, The 20-bit word stored into RTCPH, RTCPL registers is loaded in RTCD. Figure 53 : DIVIDER Counters RTCDH ...
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RTCAH & RTCAL: RTC ALARM Registers When the programmable counters reach the 32-bit value stored into RTCAH & RTCAL registers, an alarm is triggered and the interrupt request RTAIR is generated. Those registers are not protected. RTCAL (EC12h) ...
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ST10F269-T3 Interrupt control registers are common with CAPCOM1 Unit: CC10IC (RTCSI) and CC11IC (RTCAI). CCxIC CC10IC: FF8Ch/C6h CC11IC: FF8Eh/C7h Source of interrupt Request Flag External interrupt 2 CC10IR External interrupt ...
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WATCHDOG TIMER The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from malfunctioning for long periods of time. The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in ...
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ST10F269-T3 The PONR flag of WDTCON register is set if the output voltage of the internal 2.7V supply falls below the threshold (typically 2V) of the power-on detection circuit. This circuit is efficient to detect major failures of the external ...
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SYSTEM RESET System reset initializes the MCU in a predefined state. There are five ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 28. Table 28 : Reset ...
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ST10F269-T3 Figure 55 : Asynchronous Reset Sequence Internal Fetch CPU Clock Asynchronous Reset Condition RSTIN RPD RSTOUT PORT0 PLL factor latch command Internal reset signal INTERNAL FETCH Flash read signal Note: 1) RSTIN rising edge to internal latch of PORT0 ...
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Figure 56 : Synchronous Reset Sequence External Fetch (RSTIN pulse > 1040 TCL) 4 TCL 12 TCL min. max. CPU Clock RSTIN RPD 200µA Discharge RSTOUT ALE RD PORT0 Internal reset signal Note 1) RSTIN rising edge to internal latch ...
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ST10F269-T3 The short hardware reset ends and the MCU restarts.To be processed as a short hardware reset, the external RSTIN signal must last a maximum of 1038 TCL (4 TCL + 10 TCL + 1024 TCL). The system configuration is ...
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Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY READY is sampled active (low) after the programmed wait states. When READY is sampled inactive ...
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ST10F269-T3 The R0-C0 components on RPD pin are mainly implemented to provide a time delay to exit Power down mode (see Chapter 19 - Power Reduction Modes). Nevertheless, they drive RPD pin level during resets and they lead to different ...
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Figure 59 : Minimum External Reset Circuitry V DD ST10F269 R0 RPD + C0 Figure 60 : External Reset Hardware Circuitry V DD RSTOUT R0 ST10F269 RPD + C0 Table 29 : PORT0 Latched Configuration for the Different Resets X: ...
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ST10F269- POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction have been implemented in the ST10F269-T3. In Idle mode only CPU is stopped, while peripheral still operate. In Power Down mode both CPU ...
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EXICON (F1C0h / E0h EXI7ES EXI6ES RW RW EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7... Fast external interrupts disabled: standard mode EXxIN pin not taken in account for entering/exiting Power Down mode. ...
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ST10F269-T3 Figure 62 : Simplified Powerdown Exit Circuitry enter PowerDown external interrupt reset Figure 63 : Powerdown Exit Sequence When Using an External Interrupt (PLL x 2) XTAL1 CPU clk Internal Powerdown signal External Interrupt RPD ExitPwrd (internal) 116/162 V ...
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SPECIAL FUNCTION REGISTER OVERVIEW The following table lists all SFRs which are implemented in the ST10F269-T3 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked ...
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ST10F269-T3 Table 31 : Special Function Registers Listed by Name (continued) Physical Name address CC9 FE92h CC9IC b FF8Ah CC10 FE94h CC10IC b FF8Ch CC11 FE96h CC11IC b FF8Eh CC12 FE98h CC12IC b FF90h CC13 FE9Ah CC13IC b FF92h CC14 ...
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Table 31 : Special Function Registers Listed by Name (continued) Physical Name address CC30 FE7Ch CC30IC b F18Ch E CC31 FE7Eh CC31IC b F194h E CCM0 b FF52h CCM1 b FF54h CCM2 b FF56h CCM3 b FF58h CCM4 b FF22h ...
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ST10F269-T3 Table 31 : Special Function Registers Listed by Name (continued) Physical Name address MRW b FFDAh MSW b FFDEh ODP2 b F1C2h E ODP3 b F1C6h E ODP4 b F1CAh E ODP6 b F1CEh E ODP7 b F1D2h E ...
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Table 31 : Special Function Registers Listed by Name (continued) Physical Name address PP0 F038h E PP1 F03Ah E PP2 F03Ch E PP3 F03Eh E PSW b FF10h PT0 F030h E PT1 F032h E PT2 F034h E PT3 F036h E ...
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ST10F269-T3 Table 31 : Special Function Registers Listed by Name (continued) Physical Name address T0 FE50h T01CON b FF50h T0IC b FF9Ch T0REL FE54h T1 FE52h T1IC b FF9Eh T1REL FE56h T2 FE40h T2CON b FF40h T2IC b FF60h T3 ...
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... The ST10F269-T3 has four Identification registers, mapped in ESFR space. These register contain: – A manufacturer identifier, – A chip identifier, with its revision, – A internal memory and size identifier and programming voltage description. 1 IDMANUF (F07Eh / 3Fh MANUF Manufacturer Identifier - 020h: STMicroelectronics Manufacturer (JTAG worldwide normalization). 1 IDCHIP (F07Ch / 3Eh REVID Device Revision Identifier CHIPID Device Identifier - 10Dh: ST10F269-T3 identifier ...
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ST10F269-T3 20.2 - System Configuration Registers The ST10F269-T3 has registers used for different configuration of the overall system. These registers are described below. SYSCON (FF12h / 89h STKSZ ROMS1 SGTDIS ROMEN BYTDIS CLKEN WRCFG ...
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WRCFG Write Configuration Control (Inverted copy of bit WRC of RP0H) ‘0’: Pins WR and BHE retain their normal function ‘1’: Pin WR acts as WRL, pin BHE acts as WRH. CLKEN System Clock Output Enable (CLKOUT) ‘0’: CLKOUT disabled: ...
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ST10F269-T3 BUSCON4 (FF1Ah / 8Dh CSWEN4 CSREN4 RDYPOL4 RDYEN4 Notes: 1. BTYP (bit 6 and 7) are set according to the configuration of the bit l6 and l7 of PORT0 latched at the end ...
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RP0H (F108h / 84h Write Configuration Control WRC ‘0’: Pin WR acts as WRL, pin BHE acts as WRH ‘1’: Pins WR and BHE retain their normal function 2 ...
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ST10F269-T3 EXICON (F1C0h / E0h EXI7ES EXI6ES RW RW EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7... Fast external interrupts disabled: standard mode EXxIN pin not taken in account for entering/exiting Power Down ...
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Bit GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority ILVL Interrupt Priority ...
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ST10F269-T3 When both CAN are disabled via XPERCON setting, then any access in the address range 00’EE00h - 00’EFFFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. P4.4 and P4.7 can ...
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ELECTRICAL CHARACTERISTICS 21.1 - Absolute Maximum Ratings Symbol V Voltage on V pins with respect to ground Voltage on any pin with respect to ground IO V Voltage on V pin with respect to ground ...
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ST10F269-T3 Symbol Output high voltage (PORT0, PORT1, Port4 ALE, RD, WR, BHE, CLKOUT, RSTOUT Output high voltage (all other outputs) OH1 ⎥ I OZ1 CC Input leakage current (Port 5) ⎥ ⎥ I OZ2 CC ...
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This results in increased impedance of the driver, which attenuates electrical noise from the connected PCB tracks. The current specified in column “Test Conditions” is delivered in any cases. 2. This specification is not valid for outputs which ...
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ST10F269-T3 21.3.1 - A/D Converter Characteristics , ± 10 Table 32 : A/D Converter Characteristics Symbol V SR Analog Reference voltage AREF V SR Analog input voltage AIN I CC ...
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Conversion Timing Control When a conversion is capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as the sample time ...
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ST10F269-T3 21 characteristics 21.4.1 - Test Waveforms Figure 65 : Input / Output Waveforms 2.4V 0.45V AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’. Timing measurements are made ...
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The mechanism used to generate the CPU clock is selected during reset by the logic levels on pins P0.15-13 (P0H.7-5). Figure 67 : Generation Mechanisms for the CPU Clock Phase locked loop operation f XTAL f CPU Direct Clock Drive ...
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ST10F269-T3 21.4.4 - Prescaler Operation When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the internal oscillator (input clock signal 2:1 prescaler. The frequency half the frequency of CPU f ...
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The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f locked The relative deviation of TCL is XTAL the maximum when it is referred to one TCL period. It decreases ...
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ST10F269-T3 Figure 69 : External Clock Drive XTAL1 21.4.9 - Memory Cycle Variables The tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, ...
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Multiplexed Bus = 5V ± ALE cycle time = 6 TCL + 2t A Table 35 : Multiplexed Bus Characteristics Symbol Parameter t ALE high time ...
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ST10F269-T3 Table 35 : Multiplexed Bus Characteristics Symbol Parameter t Address/Unlatched CS hold 27 after RD ALE falling edge to Latched Latched CS low to Valid Data Latched CS ...
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Figure 70 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT ALE t 6 CSx A23-A16 (A15-A8) BHE Read Cycle Address/Data Bus (P0) RD Write Cycle Address/Data Bus (P0) WR WRL WRH t ...
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ST10F269-T3 Figure 71 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE CLKOUT t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 Address/Data Bus (P0) RD Write Cycle ...
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Figure 72 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT ALE t A23-A16 (A15-A8) BHE Read Cycle Address/Data Bus (P0) RdCSx Write Cycle Address/Data Bus (P0) WrCSx ...
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ST10F269-T3 Figure 73 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t ALE t 6 A23-A16 (A15-A8) BHE Read Cycle t 6 Address/Data Bus (P0) RdCSx Write ...
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Demultiplexed Bus = 5V ± ALE cycle time = 4 TCL + 2t A Table 36 : Demultiplexed Bus Characteristics Symbol Parameter t CC ALE high time 5 t ...
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ST10F269-T3 Table 36 : Demultiplexed Bus Characteristics Symbol Parameter t CC Latched CS hold after RD Address setup to RdCS, 82 WrCS (with RW-delay Address setup to RdCS, 83 WrCS (no RW-delay ...
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Figure 74 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT ALE CSx A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RD Write Cycle Data Bus (P0) (D15-D8) D7-D0 WR ...
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ST10F269-T3 Figure 75 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Extended ALE CLKOUT t ALE t CSx A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RD Write Cycle Data Bus (P0) ...
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Figure 76 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT ALE A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RdCSx Write Cycle Data Bus ...
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ST10F269-T3 Figure 77 : External Memory Cycle: Demultiplexed Bus, no Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t ALE A23-A16 A15-A0 (P1) BHE Read Cycle Data Bus (P0) (D15-D8) D7-D0 RdCSx Write Cycle Data Bus ...
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CLKOUT and READY = 5V ± Table 37 : CLKOUT and READY Characteristics Symbol Parameter t CC CLKOUT cycle time CLKOUT high time ...
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ST10F269-T3 Figure 78 : CLKOUT and READY t 32 CLKOUT ALE RD, WR Synchronous READY t 58 Asynchronous READY 3) Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the ...
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External Bus Arbitration = 5V ± Symbol Parameter t HOLD input setup time CLKOUT t CLKOUT to HLDA high BREQ low delay t ...
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ST10F269-T3 Figure 80 : External Bus Arbitration (Regaining the Bus) CLKOUT HOLD HLDA t 62 BREQ CSx (On P6.x) Other Signals Notes: 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated ...
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High-Speed Synchronous Serial Interface (SSC) Timing 21.4.14.1 Master Mode ±10 0V, CPU clock = 32MHz Symbol Parameter t CC SSC clock cycle time 300 t CC SSC clock high time ...
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ST10F269-T3 21.4.14.2 Slave mode ±10 0V, CPU clock = 32MHz Symbol Parameter t SR SSC clock cycle time 310 t SR SSC clock high time 311 t SR SSC clock low time ...
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PACKAGE INFORMATION To meet environmental requirements, ST offers this device in different grades of ECOPACK® packages, depending on environmental compliance. Figure 83 : Package Outline LQFP144 ( 1.40 mm) 144 Dimensions Minimum ...
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ST10F269- ORDERING INFORMATION Salestype ST10F269-T3 160/162 Temperature range -40° 125°C Package LQFP144 ( 1.40 mm) ...
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DATASHEET VERSION INFORMATION Date Revision Mar-2003 1 29-Jan-2009 2 Description of change Initial release Added document revision number on page 1. Replaced TQFP with LQFP throughout document. Added ECOPACK® information. Added datasheet version information. ST10F269-T3 161/162 ...
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