ST10F269Z2Q6 STMicroelectronics, ST10F269Z2Q6 Datasheet - Page 139

• Manufacturer Part Number: ST10F269Z2Q6
• Description: MCU 16BIT 256K FLASH 144PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F269Z2Q6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Controller Family/series: ST10
• No. Of I/o's: 111
• Ram Memory Size: 12KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Embedded Interface Type: CAN, SSC, USART
• Rohs Compliant: Yes
• Processor Series: ST10F26x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 12 KB
• Interface Type: CAN, SSC, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 0.3 V to 4 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4833

The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes f
locked on f
the maximum when it is referred to one TCL
period. It decreases according to the formula and
to the Figure 68 given below. For N periods of TCL
the minimum value is computed using the
corresponding deviation D
Figure 68 : Approximated Maximum PLL Jitter
21.4.8 - External Clock Drive XTAL1
V
Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 32MHz is the maximum input
Oscillator period
High time
Low time
Rise time
Fall time
DD
= 5V ± 10%, V
frequency when using an external crystal oscillator. However, 32MHz can be applied with an external clock source.
2. The input clock signal must reach the defined levels V
Parameter
±4
±3
±2
±1
Max.jitter [%]
TCL
XTAL
MIN
2
D
. The relative deviation of TCL is
N
=
=
SS
4
( ±
TCL
4 N
= 0V, T
t
t
t
t
t
OSC
1
2
3
4
Symbol
–
NOM
N
⁄
:
SR
SR
SR
SR
SR
15 ) %
A
8
×
= -40 to +125 °C
[ ]
⎛
⎜
⎜
⎝
1
Minimum Maximum Minimum
31.25
–
12.5
12.5
CPU
------------ -
100
–
–
D
f
CPU
N
2
2
1
to keep it
⎞
⎟
⎟
⎠
= f
XTAL
16
3.125
3.125
–
–
–
IL
and V
2
2
IH2
where N = number of consecutive TCL periods
and 1 ≤ N ≤ 40. So for a period of 3 TCL periods (N
= 3):
D
3TCL
3TCL
This is especially important for bus cycles using wait
states and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer
periods (e.g. pulse train generation or measurement,
lower Baud rates, etc.) the deviation caused by the
PLL jitter is negligible.
This approximated formula is valid for
1 ≤ N ≤ 40 and 10MHz ≤ f
15.625
.
3
6.25
6.25
f
CPU
–
–
min
min
2
2
= f
XTAL
Maximum Minimum Maximum
1.56
1.56
=
=
=
=
/ 2
–
–
–
2
2
4 - 3/15 = 3.8%
3TCL
3TCL
45.1ns (at f
31.25 x N
CPU
F = 1.5/2,/2.5/3/4/5
NOM
NOM
12.5
12.5
f
CPU
–
–
32
≤ 32MHz.
2
2
x (1 - 3.8/100)
x 0.962
= f
CPU
N
XTAL
= 32MHz)
ST10F269-T3
3.125
3.125
x F
–
–
–
2
2
139/162
Unit
ns
ns
ns
ns
ns