M30262F6GP#U3 Renesas Electronics America, M30262F6GP#U3 Datasheet - Page 11

• Manufacturer Part Number: M30262F6GP#U3
• Description: IC M16C/TINY MCU FLASH 48LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/26r

Specifications of M30262F6GP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 38
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/26 Group
Rev.1.00
REJ09B0176-0100Z
2. Central Processing Unit (CPU)
Figure 2.1. Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
2.2 Address Registers (A0 and A1)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.
The register A0 consists of 16 bits, and is used for address register indirect addressing and address regis-
ter relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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Note: These registers comprise a register bank. There are two register banks.
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R2
R3
b15
IPL
b19
b19
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
INTBH
b15
b15
b15
b15
R0H(R0's high bits)
R1H(R1's high bits)R1L(R1's low bits)
b8
b7
U
PC
I
INTBL
USP
ISP
FLG
R2
R3
SB
b8 b7
A0
A1
FB
O
R0L(R0's low bits)
B
S
Z
D
C
b0
b0
b0
b0
b0
b0
Interrupt table register
Flag register
Data registers (Note)
Address registers (Note)
Frame base registers (Note)
Program counter
User stack pointer
Interrupt stack pointer
Static base register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
2. CPU