MC9S12XDT256MAA Freescale Semiconductor, MC9S12XDT256MAA Datasheet - Page 912

• Manufacturer Part Number: MC9S12XDT256MAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256MAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 80-QFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 16KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Operating Supply Voltage: 0 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
914
Register
PORTB
PORTA
DDR
Name
DDRA
DDRB
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1. Always “0” on Port A, B, C, D, E, K, AD0, and AD1.
2. Applicable only on Port P, H, and J.
W
W
W
W
R
R
R
R
IO
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
DDRA7
DDRB7
All register bits in this module are completely synchronous to internal
clocks during a register read.
Bit 7
PB7
PA7
RDR
x
x
x
x
x
x
x
0
0
1
1
0
0
1
1
= Unimplemented or Reserved
DDRA6
DDRB6
PB6
PA6
Figure 23-2. PIM Register Summary (Sheet 1 of 7)
PE
0
1
1
0
0
1
1
x
x
x
x
x
x
x
x
6
Table 23-3. Pin Configuration Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
PS
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
DDRA5
DDRB5
1
PB5
PA5
5
IE
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2
NOTE
DDRA4
DDRB4
PB4
PA4
Input
Input
Input
Input
Input
Input
Input
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
4
Function
DDRA3
DDRB3
PB3
PA3
3
DDRA2
DDRB2
PB2
PA2
2
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Pull Device
Freescale Semiconductor
DDRA1
DDRB1
PA1
PB1
1
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Interrupt
DDRA0
DDRB0
Bit 0
PB0
PA0