SAF-TC1130-L150EB-G BB Infineon Technologies, SAF-TC1130-L150EB-G BB Datasheet - Page 104

• Manufacturer Part Number: SAF-TC1130-L150EB-G BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB-G BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 144 KB
• Interface Type: 3xASC, 2xSSC, I2C, 2xMLI, Ethernet 10, 100 Mbits, s, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 9
• Operating Supply Voltage: 1.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-LBGA-208
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 144.0 KByte
• Can Nodes: 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: FT1130L150EBGBBXP; SAF-TC1130-L150EB-GBB; SAF-TC1130-L150EB-GBBINTR; SAF-TC1130-L150EB-GBBTR; SAF-TC1130-L150EB-GBBTR; SAFTC1130L150EBBBXT; SP000106119; SP000106538; SP000743584

4.3.8.5
(Operating Conditions apply; C
Parameter
CSx, RD/WR, RD, MR/W, BC(3:0) output valid time
from output clock
CSx, RD/WR, RD, MR/W, BC(3:0) output hold time
from output clock
Address output valid time from output clock
Address output hold time from output clock
WAIT input setup time to output clock
WAIT input hold time from output clock
AD(31:0) output valid time from output clock
AD(31:0) output hold time from output clock
AD(31:0) input setup time to output clock
AD(31:0) input hold time from output clock
RMW output valid time from output clock
RMW output hold time from output clock
AD(31:0) output hold time from RD/WR
1) The purpose for characterization of Asynchronous access is to provide the performance of all of the signals to
Data Sheet
user. User can decide whether an extra cycle is needed or not based on above parameters to generate signals
with correct timing sequence. It is user’s responsibility to program the correct phase length according to the
memory/peripheral device specification and EBU specification.
Timing for Demultiplexed Access Signals
L
= 50 pF)
1)
98
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
7
8
9
10
11
12
13
14
16
CC −
CC 0.0
CC −
CC 0.0
CC −
CC 0.0
CC −
CC 1.3
CC 0
SR 12
SR 3
SR 1.3
SR 3
Electrical Parameters
min
Limits
9
−
9
−
−
−
9
−
−
−
8
−
−
max
V1.1, 2008-12
TC1130
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns