SAF-TC1130-L150EB-G BB Infineon Technologies, SAF-TC1130-L150EB-G BB Datasheet - Page 19

• Manufacturer Part Number: SAF-TC1130-L150EB-G BB
• Description: IC MCU 32BIT TRICOR 16KB LBGA208
• Manufacturer: Infineon Technologies
• Series: TC11xxr

Specifications of SAF-TC1130-L150EB-G BB

• Core Processor: TriCore
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Type: ROMless
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LSBGA
• Data Bus Width: 32 bit
• Program Memory Size: 32 KB
• Data Ram Size: 144 KB
• Interface Type: 3xASC, 2xSSC, I2C, 2xMLI, Ethernet 10, 100 Mbits, s, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 72
• Number Of Timers: 9
• Operating Supply Voltage: 1.5 V, 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Packages: PG-LBGA-208
• Max Clock Frequency: 150.0 MHz
• Sram (incl. Cache): 144.0 KByte
• Can Nodes: 4
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: FT1130L150EBGBBXP; SAF-TC1130-L150EB-GBB; SAF-TC1130-L150EB-GBBINTR; SAF-TC1130-L150EB-GBBTR; SAF-TC1130-L150EB-GBBTR; SAFTC1130L150EBBBXT; SP000106119; SP000106538; SP000743584

Table 2-1
Symbol
P3.11
P3.12
P3.13
P3.14
P3.15
Data Sheet
Pin
C16
D16
K13
J14
J15
Pin Definitions and Functions (cont’d)
In
Out
O
O
O
I
O
I
O
I
O
O
I/O
O
I
I/O
O
I
I/O
PU/
PD
PUC
PUC
PUC
PUC
PUC
1)
Functions
OCDSB_11
TDATA1
SLSO0_7
CC61_T12HR CCU61 Timer 12 hardware run
OCDSB_12
RCLK1
SLSO1_7
CC61_T13HR CCU61 Timer 13 hardware run
OCDSB_13
RREADY1
MRST1B
OCDSB_14
RVALID1
MTSR1B
OCDSB_15
RDATA1
SCLK1B
13
OCDS L2 Debug Line B11
MLI1 transmit channel data output
SSC0 Slave Select output 7
OCDS L2 Debug Line B12
MLI1 receive channel clock input
SSC1 Slave Select output 7
OCDS L2 Debug Line B13
MLI1 receive channel ready output
SSC1 master receive/slave
OCDS L2 Debug Line B14
MLI1 receive channel valid input
SSC1 master transmit/slave
OCDS L2 Debug Line B15
MLI1 receive channel data input
SSC1 clock input/output line B
transmit input/output B
receive input/output B
General Device Information
V1.1, 2008-12
TC1130