PIC17C756-33I/L Microchip Technology, PIC17C756-33I/L Datasheet - Page 170

• Manufacturer Part Number: PIC17C756-33I/L
• Description: MICRO CTRL 16K MEMORY OTP 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33I/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• For Use With: AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

16.1
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 16-4. The source
impedance (R
impedance directly affect the time required to charge
the capacitor C
impedance varies over the device voltage (V
Figure 16-4. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
The maximum recommended impedance for ana-
log sources is 10 k . After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
To
Equation 16-1 may be used. This equation calculates
the acquisition time to within 1/2 LSb error (1024 steps
for the A/D). The 1/2 LSb error is the maximum error
allowed for the A/D to meet its specified accuracy.
EQUATION 16-1:
V
given V
or
Tcap = -(200 pF)(1 k + R
FIGURE 16-4: ANALOG INPUT MODEL
DS30264A-page 170
HOLD
calculate
= (V
V
HOLD
REF
A/D Acquisition Requirements
REF
= V
= (V
- (V
S
REF
) and the internal sampling switch (R
REF
REF
HOLD
the
+ - V
Legend C
/2048)) • (1 - e
/2048), for 1/2 LSb resolution
VA
REF
SS
. The sampling switch (R
A/D MINIMUM CHARGING
TIME (FOR C
minimum
+ R
Rs
-
V
I leakage
R
SS
C
T
PIN
IC
HOLD
S
) ln(1/2047)
ANx
C
5 pF
HOLD
(-Tcap/C
PIN
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
acquisition
) must be allowed
HOLD
HOLD
(R
IC
)
+ R
V
DD
SS
+ R
V
V
time,
T
DD
T
Preliminary
SS
SS
S
= 0.6V
= 0.6V
))
),
)
)
)
I leakage
500 nA
Example 16-1 shows the calculation of the minimum
required acquisition time T
based on the following application system assump-
tions.
C
Rs = 10 k
1/2 LSb error
V
Temp (application system max.) = 50 C
V
R
HOLD
DD
HOLD
IC
Note 1: The reference voltage (V
Note 2: The charge holding capacitor (C
Note 3: The maximum recommended impedance
Note 4: After a conversion has completed, a
= 5V
1k
= 0 @ t = 0
= 200 pF
V
SS R
DD
Sampling
Switch
effect on the equation, since it cancels
itself out.
not discharged after each conversion.
for analog sources is 10 k . This is
required to meet the pin leakage specifi-
cation.
2.0T
sition can begin again. During this time the
holding capacitor is not connected to the
selected A/D input channel.
Rss = 7 k
6V
5V
4V
3V
2V
SS
AD
delay must complete before acqui-
Sampling Switch
5 6 7 8 9 10 11
V
SS
C
= DAC capacitance
= 200 pF
( k )
HOLD
1997 Microchip Technology Inc.
ACQ
. This calculation is
REF
) has no
HOLD
) is